[llvm-commits] CVS: llvm/utils/TableGen/AsmWriterEmitter.cpp AsmWriterEmitter.h CodeGenTarget.cpp TableGen.cpp

[Chris Lattner]

Changes in directory llvm/utils/TableGen:

AsmWriterEmitter.cpp added (r1.1)
AsmWriterEmitter.h added (r1.1)
CodeGenTarget.cpp updated: 1.10 -> 1.11
TableGen.cpp updated: 1.31 -> 1.32

---
Log message:

Initial cut at an asm writer emitter.  So far, this only handles emission of
instructions, and only instructions that take no operands at that!


---
Diffs of the changes:  (+99 -3)

Index: llvm/utils/TableGen/AsmWriterEmitter.cpp
diff -c /dev/null llvm/utils/TableGen/AsmWriterEmitter.cpp:1.1
*** /dev/null	Sun Aug  1 00:59:43 2004
--- llvm/utils/TableGen/AsmWriterEmitter.cpp	Sun Aug  1 00:59:33 2004
***************
*** 0 ****
--- 1,48 ----
+ //===- AsmWriterEmitter.cpp - Generate an assembly writer -----------------===//
+ // 
+ //                     The LLVM Compiler Infrastructure
+ //
+ // This file was developed by the LLVM research group and is distributed under
+ // the University of Illinois Open Source License. See LICENSE.TXT for details.
+ // 
+ //===----------------------------------------------------------------------===//
+ //
+ // This tablegen backend is emits an assembly printer for the current target.
+ // Note that this is currently fairly skeletal, but will grow over time.
+ //
+ //===----------------------------------------------------------------------===//
+ 
+ #include "AsmWriterEmitter.h"
+ #include "CodeGenTarget.h"
+ #include <ostream>
+ using namespace llvm;
+ 
+ void AsmWriterEmitter::run(std::ostream &O) {
+   EmitSourceFileHeader("Assembly Writer Source Fragment", O);
+ 
+   CodeGenTarget Target;
+   O <<
+   "/// printInstruction - This method is automatically generated by tablegen\n"
+   "/// from the instruction set description.  This method returns true if the\n"
+   "/// machine instruction was sufficiently described to print it, otherwise\n"
+   "/// it returns false.\n"
+     "bool " << Target.getName()
+             << "AsmPrinter::printInstruction(const MachineInstr *MI) {\n";
+   O << "  switch (MI->getOpcode()) {\n"
+        "  default: return false;\n";
+ 
+   std::string Namespace = Target.inst_begin()->second.Namespace;
+ 
+   for (CodeGenTarget::inst_iterator I = Target.inst_begin(),
+          E = Target.inst_end(); I != E; ++I)
+     if (!I->second.AsmString.empty()) {
+       const std::string &AsmString = I->second.AsmString;
+       O << "  case " << Namespace << "::" << I->first << ": O << \""
+         << AsmString << "\" << '\\n'; break;\n";
+     }
+ 
+   O << "  }\n"
+        "  return true;\n"
+        "}\n";
+   EmitSourceFileTail(O);
+ }


Index: llvm/utils/TableGen/AsmWriterEmitter.h
diff -c /dev/null llvm/utils/TableGen/AsmWriterEmitter.h:1.1
*** /dev/null	Sun Aug  1 00:59:43 2004
--- llvm/utils/TableGen/AsmWriterEmitter.h	Sun Aug  1 00:59:33 2004
***************
*** 0 ****
--- 1,31 ----
+ //===- AsmWriterEmitter.h - Generate an assembly writer ---------*- C++ -*-===//
+ // 
+ //                     The LLVM Compiler Infrastructure
+ //
+ // This file was developed by the LLVM research group and is distributed under
+ // the University of Illinois Open Source License. See LICENSE.TXT for details.
+ // 
+ //===----------------------------------------------------------------------===//
+ //
+ // This tablegen backend is responsible for emitting an assembly printer for the
+ // code generator.
+ //
+ //===----------------------------------------------------------------------===//
+ 
+ #ifndef ASMWRITER_EMITTER_H
+ #define ASMWRITER_EMITTER_H
+ 
+ #include "TableGenBackend.h"
+ 
+ namespace llvm {
+ 
+   class AsmWriterEmitter : public TableGenBackend {
+     RecordKeeper &Records;
+   public:
+     AsmWriterEmitter(RecordKeeper &R) : Records(R) {}
+     
+     // run - Output the asmwriter, returning true on failure.
+     void run(std::ostream &o);
+   };
+ }
+ #endif


Index: llvm/utils/TableGen/CodeGenTarget.cpp
diff -u llvm/utils/TableGen/CodeGenTarget.cpp:1.10 llvm/utils/TableGen/CodeGenTarget.cpp:1.11
--- llvm/utils/TableGen/CodeGenTarget.cpp:1.10	Sun Aug  1 00:04:00 2004
+++ llvm/utils/TableGen/CodeGenTarget.cpp	Sun Aug  1 00:59:33 2004
@@ -122,14 +122,23 @@
   Namespace = R->getValueAsString("Namespace");
   AsmString = R->getValueAsString("AsmString");
 
-  //TODO: Parse OperandList
-  
   isReturn     = R->getValueAsBit("isReturn");
   isBranch     = R->getValueAsBit("isBranch");
   isBarrier    = R->getValueAsBit("isBarrier");
   isCall       = R->getValueAsBit("isCall");
   isTwoAddress = R->getValueAsBit("isTwoAddress");
   isTerminator = R->getValueAsBit("isTerminator");
+
+
+  //TODO: Parse OperandList
+  try {
+    DagInit *DI = R->getValueAsDag("OperandList");
+
+    // Cannot handle instructions with operands yet.
+    if (DI->getNumArgs())
+      AsmString.clear();
+  } catch (...) {
+  }
 }
 
 


Index: llvm/utils/TableGen/TableGen.cpp
diff -u llvm/utils/TableGen/TableGen.cpp:1.31 llvm/utils/TableGen/TableGen.cpp:1.32
--- llvm/utils/TableGen/TableGen.cpp:1.31	Sat Jul 31 22:55:38 2004
+++ llvm/utils/TableGen/TableGen.cpp	Sun Aug  1 00:59:33 2004
@@ -22,6 +22,7 @@
 #include "CodeEmitterGen.h"
 #include "RegisterInfoEmitter.h"
 #include "InstrInfoEmitter.h"
+#include "AsmWriterEmitter.h"
 #include "InstrSelectorEmitter.h"
 #include <algorithm>
 #include <cstdio>
@@ -32,7 +33,7 @@
   PrintRecords,
   GenEmitter,
   GenRegisterEnums, GenRegister, GenRegisterHeader,
-  GenInstrEnums, GenInstrs, GenInstrSelector,
+  GenInstrEnums, GenInstrs, GenAsmWriter, GenInstrSelector,
   PrintEnums,
   Parse
 };
@@ -54,6 +55,8 @@
                                "Generate enum values for instructions"),
                     clEnumValN(GenInstrs, "gen-instr-desc",
                                "Generate instruction descriptions"),
+                    clEnumValN(GenAsmWriter, "gen-asm-writer",
+                               "Generate assembly writer"),
                     clEnumValN(GenInstrSelector, "gen-instr-selector",
                                "Generate an instruction selector"),
                     clEnumValN(PrintEnums, "print-enums",
@@ -454,6 +457,11 @@
     case GenInstrs:
       InstrInfoEmitter(Records).run(*Out);
       break;
+
+    case GenAsmWriter:
+      AsmWriterEmitter(Records).run(*Out);
+      break;
+
     case GenInstrSelector:
       InstrSelectorEmitter(Records).run(*Out);
       break;