[llvm-commits] CVS: llvm/lib/Target/SparcV8/SparcV8RegisterInfo.td

[Chris Lattner]

On Sun, 7 Mar 2004, Alkis Evlogimenos wrote:

> >  // FIXME: the register order should be defined in terms of the preferred
> >  // allocation order...
> >  //
> > -def IntRegs : RegisterClass<i32, 8, [G1, G2, G3, G4, G5, G6, G7, G0,
> > -                                     O0, O1, O2, O3, O4, O5, O6, O7,
> > +def IntRegs : RegisterClass<i32, 8, [G1, G2, G3, G4, G5, G6, G7,
> > +                                     O0, O1, O2, O3, O4, O5, O7,
> >                                       L0, L1, L2, L3, L4, L5, L6, L7,
> > -                                     I0, I1, I2, I3, I4, I5, I6, I7]>;
> > +                                     I0, I1, I2, I3, I4, I5,
> > +                                     // Non-allocatable regs
> > +                                     O6, I6, I7, G0]> {
> > +  let Methods = [{
> > +    iterator allocation_order_end(MachineFunction &MF) const {
> > +      return end()-4;  // Don't allocate special registers
> > +    }
> > +  }];
> > +}

> Maybe G0 should be placed back in IntRegs and allocation order begin should start at the second element?

The real fix is to take G0 *out* of the i32 class.  I'm not sure if this
is possible, but none of the X86 reserved registers (e.g., ESP) are
included in the i32 register class.

There's no need to get the registers in a particular order (which would
prefer G0 at the front of the list), and, in fact, the elements should be
reordered in the preferred allocation order anyway.  As such, I don't see
a need to move it...

-Chris

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