[llvm-commits] CVS: llvm/lib/Target/SparcV8/SparcV8RegisterInfo.td

[Alkis Evlogimenos]

On Sunday 07 March 2004 09:48 pm, Chris Lattner wrote:
> 
> Changes in directory llvm/lib/Target/SparcV8:
> 
> SparcV8RegisterInfo.td updated: 1.6 -> 1.7
> 
> ---
> Log message:
> 
> Avoid allocating special registers a bit more robustly
> 
> 
> ---
> Diffs of the changes:  (+11 -3)
> 
> Index: llvm/lib/Target/SparcV8/SparcV8RegisterInfo.td
> diff -u llvm/lib/Target/SparcV8/SparcV8RegisterInfo.td:1.6 llvm/lib/Target/SparcV8/SparcV8RegisterInfo.td:1.7
> --- llvm/lib/Target/SparcV8/SparcV8RegisterInfo.td:1.6	Fri Mar  5 23:31:32 2004
> +++ llvm/lib/Target/SparcV8/SparcV8RegisterInfo.td	Sun Mar  7 21:48:07 2004
> @@ -61,10 +61,18 @@
>  // FIXME: the register order should be defined in terms of the preferred
>  // allocation order...
>  //
> -def IntRegs : RegisterClass<i32, 8, [G1, G2, G3, G4, G5, G6, G7, G0,
> -                                     O0, O1, O2, O3, O4, O5, O6, O7,
> +def IntRegs : RegisterClass<i32, 8, [G1, G2, G3, G4, G5, G6, G7,
> +                                     O0, O1, O2, O3, O4, O5, O7,
>                                       L0, L1, L2, L3, L4, L5, L6, L7,
> -                                     I0, I1, I2, I3, I4, I5, I6, I7]>;
> +                                     I0, I1, I2, I3, I4, I5,
> +                                     // Non-allocatable regs
> +                                     O6, I6, I7, G0]> {
> +  let Methods = [{
> +    iterator allocation_order_end(MachineFunction &MF) const {
> +      return end()-4;  // Don't allocate special registers
> +    }
> +  }];
> +}
>  
>  def FPRegs : RegisterClass<f32, 4, [F0, F1, F2, F3, F4, F5, F6, F7, F8,
>    F9, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F20, F21, F22,
> 

Maybe G0 should be placed back in IntRegs and allocation order begin should start at the second element?

-- 

Alkis