[llvm-commits] CVS: llvm/lib/Target/SparcV8/SparcV8RegisterInfo.cpp SparcV8RegisterInfo.td

[Chris Lattner]

Changes in directory llvm/lib/Target/SparcV8:

SparcV8RegisterInfo.cpp updated: 1.2 -> 1.3
SparcV8RegisterInfo.td updated: 1.2 -> 1.3

---
Log message:

Implement initial prolog/epilog code insertion methods.


---
Diffs of the changes:  (+17 -6)

Index: llvm/lib/Target/SparcV8/SparcV8RegisterInfo.cpp
diff -u llvm/lib/Target/SparcV8/SparcV8RegisterInfo.cpp:1.2 llvm/lib/Target/SparcV8/SparcV8RegisterInfo.cpp:1.3
--- llvm/lib/Target/SparcV8/SparcV8RegisterInfo.cpp:1.2	Sat Feb 28 13:37:18 2004
+++ llvm/lib/Target/SparcV8/SparcV8RegisterInfo.cpp	Sat Feb 28 23:18:30 2004
@@ -13,7 +13,10 @@
 
 #include "SparcV8.h"
 #include "SparcV8RegisterInfo.h"
+#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/Type.h"
+#include "Support/STLExtras.h"
 using namespace llvm;
 
 SparcV8RegisterInfo::SparcV8RegisterInfo()
@@ -60,18 +63,23 @@
   abort();
 }
 
-void SparcV8RegisterInfo::processFunctionBeforeFrameFinalized(
-    MachineFunction &MF) const {
-  abort();
-}
+void SparcV8RegisterInfo::
+processFunctionBeforeFrameFinalized(MachineFunction &MF) const {}
 
 void SparcV8RegisterInfo::emitPrologue(MachineFunction &MF) const {
-  abort();
+  MachineBasicBlock &MBB = MF.front();
+
+  // Eventually this should emit the correct save instruction based on the
+  // number of bytes in the frame.  For now we just hardcode it.
+  BuildMI(MBB, MBB.begin(), V8::SAVEi, 2, V8::SP).addImm(-122).addReg(V8::SP);
 }
 
 void SparcV8RegisterInfo::emitEpilogue(MachineFunction &MF,
                                        MachineBasicBlock &MBB) const {
-  abort();
+  MachineBasicBlock::iterator MBBI = prior(MBB.end());
+  assert(MBBI->getOpcode() == V8::JMPLi &&
+         "Can only put epilog before return instruction!");
+  BuildMI(MBB, MBBI, V8::RESTOREi, 2, V8::O0).addImm(0).addReg(V8::L7);
 }
 
 


Index: llvm/lib/Target/SparcV8/SparcV8RegisterInfo.td
diff -u llvm/lib/Target/SparcV8/SparcV8RegisterInfo.td:1.2 llvm/lib/Target/SparcV8/SparcV8RegisterInfo.td:1.3
--- llvm/lib/Target/SparcV8/SparcV8RegisterInfo.td:1.2	Sat Feb 28 18:27:00 2004
+++ llvm/lib/Target/SparcV8/SparcV8RegisterInfo.td	Sat Feb 28 23:18:30 2004
@@ -26,6 +26,9 @@
   def I0 : Ri<24>;    def I1 : Ri<25>;    def I2 : Ri<26>;    def I3 : Ri<27>;
   def I4 : Ri<28>;    def I5 : Ri<29>;    def I6 : Ri<30>;    def I7 : Ri<31>;
 
+  // Standard register aliases.
+  def SP : Ri<14>;    def FP : Ri<30>;
+
   // Floating-point registers?
   // ...
 }