[llvm-commits] CVS: llvm/lib/Target/X86/X86RegisterInfo.cpp X86InstrInfo.td

[Alkis Evlogimenos]

Changes in directory llvm/lib/Target/X86:

X86RegisterInfo.cpp updated: 1.68 -> 1.69
X86InstrInfo.td updated: 1.42 -> 1.43

---
Log message:

Add memory operand folding support for SHLD and SHRD instructions.


---
Diffs of the changes:  (+15 -0)

Index: llvm/lib/Target/X86/X86RegisterInfo.cpp
diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.68 llvm/lib/Target/X86/X86RegisterInfo.cpp:1.69
--- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.68	Fri Feb 27 03:28:43 2004
+++ llvm/lib/Target/X86/X86RegisterInfo.cpp	Fri Feb 27 09:03:18 2004
@@ -98,6 +98,13 @@
                  .addReg(MI->getOperand(1).getReg());
 }
 
+static MachineInstr *MakeMRIInst(unsigned Opcode, unsigned FrameIndex,
+                                 MachineInstr *MI) {
+  return addFrameReference(BuildMI(Opcode, 5), FrameIndex)
+      .addReg(MI->getOperand(1).getReg())
+      .addZImm(MI->getOperand(2).getImmedValue());
+}
+
 static MachineInstr *MakeMIInst(unsigned Opcode, unsigned FrameIndex,
                                 MachineInstr *MI) {
   if (MI->getOperand(1).isImmediate())
@@ -215,6 +222,10 @@
     case X86::SARri8:  NI = MakeMIInst(X86::SARmi8 , FrameIndex, MI); break;
     case X86::SARri16: NI = MakeMIInst(X86::SARmi16, FrameIndex, MI); break;
     case X86::SARri32: NI = MakeMIInst(X86::SARmi32, FrameIndex, MI); break;
+    case X86::SHLDrrCL32:NI = MakeMRInst( X86::SHLDmrCL32,FrameIndex, MI);break;
+    case X86::SHLDrri32: NI = MakeMRIInst(X86::SHLDmri32, FrameIndex, MI);break;
+    case X86::SHRDrrCL32:NI = MakeMRInst( X86::SHRDmrCL32,FrameIndex, MI);break;
+    case X86::SHRDrri32: NI = MakeMRIInst(X86::SHRDmri32, FrameIndex, MI);break;
     case X86::TESTrr8: NI = MakeMRInst(X86::TESTmr8 ,FrameIndex, MI); break;
     case X86::TESTrr16:NI = MakeMRInst(X86::TESTmr16,FrameIndex, MI); break;
     case X86::TESTrr32:NI = MakeMRInst(X86::TESTmr32,FrameIndex, MI); break;


Index: llvm/lib/Target/X86/X86InstrInfo.td
diff -u llvm/lib/Target/X86/X86InstrInfo.td:1.42 llvm/lib/Target/X86/X86InstrInfo.td:1.43
--- llvm/lib/Target/X86/X86InstrInfo.td:1.42	Fri Feb 27 03:28:43 2004
+++ llvm/lib/Target/X86/X86InstrInfo.td	Fri Feb 27 09:03:18 2004
@@ -495,10 +495,14 @@
 def SARmi32  : I2A8 <"sar", 0xC1, MRMS7m    >;                 // [mem32] >>>= imm32
 
 def SHLDrrCL32 : I2A8 <"shld", 0xA5, MRMDestReg>, TB, UsesCL;   // R32 <<= R32,R32 cl
+def SHLDmrCL32 : I2A8 <"shld", 0xA5, MRMDestMem>, TB, UsesCL;   // [mem32] <<= [mem32],R32 cl
 def SHLDrri32  : I2A8 <"shld", 0xA4, MRMDestReg>, TB;           // R32 <<= R32,R32 imm8
+def SHLDmri32  : I2A8 <"shld", 0xA4, MRMDestMem>, TB;           // [mem32] <<= [mem32],R32 imm8
 
 def SHRDrrCL32 : I2A8 <"shrd", 0xAD, MRMDestReg>, TB, UsesCL;   // R32 >>= R32,R32 cl
+def SHRDmrCL32 : I2A8 <"shrd", 0xAD, MRMDestMem>, TB, UsesCL;   // [mem32] >>= [mem32],R32 cl
 def SHRDrri32  : I2A8 <"shrd", 0xAC, MRMDestReg>, TB;           // R32 >>= R32,R32 imm8
+def SHRDmri32  : I2A8 <"shrd", 0xAC, MRMDestMem>, TB;           // [mem32] >>= [mem32],R32 imm8
 
 // Condition code ops, incl. set if equal/not equal/...
 def SAHF     : X86Inst<"sahf" , 0x9E, RawFrm, Arg8>, Imp<[AH],[]>;  // flags = AH