[llvm-commits] CVS: llvm/lib/Target/X86/X86RegisterInfo.cpp X86InstrInfo.td

[Alkis Evlogimenos]

Changes in directory llvm/lib/Target/X86:

X86RegisterInfo.cpp updated: 1.67 -> 1.68
X86InstrInfo.td updated: 1.41 -> 1.42

---
Log message:

Add memory operand folding support for SHL, SHR and SAR, SHLD instructions.


---
Diffs of the changes:  (+39 -0)

Index: llvm/lib/Target/X86/X86RegisterInfo.cpp
diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.67 llvm/lib/Target/X86/X86RegisterInfo.cpp:1.68
--- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.67	Sun Feb 22 13:23:26 2004
+++ llvm/lib/Target/X86/X86RegisterInfo.cpp	Fri Feb 27 03:28:43 2004
@@ -197,6 +197,24 @@
     case X86::XORri8:  NI = MakeMIInst(X86::XORmi8 , FrameIndex, MI); break;
     case X86::XORri16: NI = MakeMIInst(X86::XORmi16, FrameIndex, MI); break;
     case X86::XORri32: NI = MakeMIInst(X86::XORmi32, FrameIndex, MI); break;
+    case X86::SHLrCL8: NI = MakeMInst( X86::SHLmCL8 ,FrameIndex, MI); break;
+    case X86::SHLrCL16:NI = MakeMInst( X86::SHLmCL16,FrameIndex, MI); break;
+    case X86::SHLrCL32:NI = MakeMInst( X86::SHLmCL32,FrameIndex, MI); break;
+    case X86::SHLri8:  NI = MakeMIInst(X86::SHLmi8 , FrameIndex, MI); break;
+    case X86::SHLri16: NI = MakeMIInst(X86::SHLmi16, FrameIndex, MI); break;
+    case X86::SHLri32: NI = MakeMIInst(X86::SHLmi32, FrameIndex, MI); break;
+    case X86::SHRrCL8: NI = MakeMInst( X86::SHRmCL8 ,FrameIndex, MI); break;
+    case X86::SHRrCL16:NI = MakeMInst( X86::SHRmCL16,FrameIndex, MI); break;
+    case X86::SHRrCL32:NI = MakeMInst( X86::SHRmCL32,FrameIndex, MI); break;
+    case X86::SHRri8:  NI = MakeMIInst(X86::SHRmi8 , FrameIndex, MI); break;
+    case X86::SHRri16: NI = MakeMIInst(X86::SHRmi16, FrameIndex, MI); break;
+    case X86::SHRri32: NI = MakeMIInst(X86::SHRmi32, FrameIndex, MI); break;
+    case X86::SARrCL8: NI = MakeMInst( X86::SARmCL8 ,FrameIndex, MI); break;
+    case X86::SARrCL16:NI = MakeMInst( X86::SARmCL16,FrameIndex, MI); break;
+    case X86::SARrCL32:NI = MakeMInst( X86::SARmCL32,FrameIndex, MI); break;
+    case X86::SARri8:  NI = MakeMIInst(X86::SARmi8 , FrameIndex, MI); break;
+    case X86::SARri16: NI = MakeMIInst(X86::SARmi16, FrameIndex, MI); break;
+    case X86::SARri32: NI = MakeMIInst(X86::SARmi32, FrameIndex, MI); break;
     case X86::TESTrr8: NI = MakeMRInst(X86::TESTmr8 ,FrameIndex, MI); break;
     case X86::TESTrr16:NI = MakeMRInst(X86::TESTmr16,FrameIndex, MI); break;
     case X86::TESTrr32:NI = MakeMRInst(X86::TESTmr32,FrameIndex, MI); break;


Index: llvm/lib/Target/X86/X86InstrInfo.td
diff -u llvm/lib/Target/X86/X86InstrInfo.td:1.41 llvm/lib/Target/X86/X86InstrInfo.td:1.42
--- llvm/lib/Target/X86/X86InstrInfo.td:1.41	Fri Feb 27 00:57:05 2004
+++ llvm/lib/Target/X86/X86InstrInfo.td	Fri Feb 27 03:28:43 2004
@@ -455,23 +455,44 @@
 def SHLrCL8  : I2A8 <"shl", 0xD2, MRMS4r    >        , UsesCL; // R8  <<= cl
 def SHLrCL16 : I2A8 <"shl", 0xD3, MRMS4r    >, OpSize, UsesCL; // R16 <<= cl
 def SHLrCL32 : I2A8 <"shl", 0xD3, MRMS4r    >        , UsesCL; // R32 <<= cl
+def SHLmCL8  : I2A8 <"shl", 0xD2, MRMS4m    >        , UsesCL; // [mem8]  <<= cl
+def SHLmCL16 : I2A8 <"shl", 0xD3, MRMS4m    >, OpSize, UsesCL; // [mem16] <<= cl
+def SHLmCL32 : I2A8 <"shl", 0xD3, MRMS4m    >        , UsesCL; // [mem32] <<= cl
+
 def SHLri8   : I2A8 <"shl", 0xC0, MRMS4r    >;                 // R8  <<= imm8
 def SHLri16  : I2A8 <"shl", 0xC1, MRMS4r    >, OpSize;         // R16 <<= imm16
 def SHLri32  : I2A8 <"shl", 0xC1, MRMS4r    >;                 // R32 <<= imm32
+def SHLmi8   : I2A8 <"shl", 0xC0, MRMS4m    >;                 // [mem8]  <<= imm8
+def SHLmi16  : I2A8 <"shl", 0xC1, MRMS4m    >, OpSize;         // [mem16] <<= imm16
+def SHLmi32  : I2A8 <"shl", 0xC1, MRMS4m    >;                 // [mem32] <<= imm32
 
 def SHRrCL8  : I2A8 <"shr", 0xD2, MRMS5r    >        , UsesCL; // R8  >>= cl
 def SHRrCL16 : I2A8 <"shr", 0xD3, MRMS5r    >, OpSize, UsesCL; // R16 >>= cl
 def SHRrCL32 : I2A8 <"shr", 0xD3, MRMS5r    >        , UsesCL; // R32 >>= cl
+def SHRmCL8  : I2A8 <"shr", 0xD2, MRMS5m    >        , UsesCL; // [mem8]  >>= cl
+def SHRmCL16 : I2A8 <"shr", 0xD3, MRMS5m    >, OpSize, UsesCL; // [mem16] >>= cl
+def SHRmCL32 : I2A8 <"shr", 0xD3, MRMS5m    >        , UsesCL; // [mem32] >>= cl
+
 def SHRri8   : I2A8 <"shr", 0xC0, MRMS5r    >;                 // R8  >>= imm8
 def SHRri16  : I2A8 <"shr", 0xC1, MRMS5r    >, OpSize;         // R16 >>= imm16
 def SHRri32  : I2A8 <"shr", 0xC1, MRMS5r    >;                 // R32 >>= imm32
+def SHRmi8   : I2A8 <"shr", 0xC0, MRMS5m    >;                 // [mem8]  >>= imm8
+def SHRmi16  : I2A8 <"shr", 0xC1, MRMS5m    >, OpSize;         // [mem16] >>= imm16
+def SHRmi32  : I2A8 <"shr", 0xC1, MRMS5m    >;                 // [mem32] >>= imm32
 
 def SARrCL8  : I2A8 <"sar", 0xD2, MRMS7r    >        , UsesCL; // R8  >>>= cl
 def SARrCL16 : I2A8 <"sar", 0xD3, MRMS7r    >, OpSize, UsesCL; // R16 >>>= cl
 def SARrCL32 : I2A8 <"sar", 0xD3, MRMS7r    >        , UsesCL; // R32 >>>= cl
+def SARmCL8  : I2A8 <"sar", 0xD2, MRMS7m    >        , UsesCL; // [mem8]  >>>= cl
+def SARmCL16 : I2A8 <"sar", 0xD3, MRMS7m    >, OpSize, UsesCL; // [mem16] >>>= cl
+def SARmCL32 : I2A8 <"sar", 0xD3, MRMS7m    >        , UsesCL; // [mem32] >>>= cl
+
 def SARri8   : I2A8 <"sar", 0xC0, MRMS7r    >;                 // R8  >>>= imm8
 def SARri16  : I2A8 <"sar", 0xC1, MRMS7r    >, OpSize;         // R16 >>>= imm16
 def SARri32  : I2A8 <"sar", 0xC1, MRMS7r    >;                 // R32 >>>= imm32
+def SARmi8   : I2A8 <"sar", 0xC0, MRMS7m    >;                 // [mem8]  >>>= imm8
+def SARmi16  : I2A8 <"sar", 0xC1, MRMS7m    >, OpSize;         // [mem16] >>>= imm16
+def SARmi32  : I2A8 <"sar", 0xC1, MRMS7m    >;                 // [mem32] >>>= imm32
 
 def SHLDrrCL32 : I2A8 <"shld", 0xA5, MRMDestReg>, TB, UsesCL;   // R32 <<= R32,R32 cl
 def SHLDrri32  : I2A8 <"shld", 0xA4, MRMDestReg>, TB;           // R32 <<= R32,R32 imm8