[llvm-commits] CVS: llvm/lib/CodeGen/TwoAddressInstructionPass.cpp RegAllocSimple.cpp RegAllocLocal.cpp RegAllocLinearScan.cpp PHIElimination.cpp MachineInstr.cpp LiveIntervals.cpp
Alkis Evlogimenos
alkis at cs.uiuc.edu
Fri Feb 13 15:02:03 PST 2004
Changes in directory llvm/lib/CodeGen:
TwoAddressInstructionPass.cpp updated: 1.14 -> 1.15
RegAllocSimple.cpp updated: 1.49 -> 1.50
RegAllocLocal.cpp updated: 1.44 -> 1.45
RegAllocLinearScan.cpp updated: 1.45 -> 1.46
PHIElimination.cpp updated: 1.16 -> 1.17
MachineInstr.cpp updated: 1.88 -> 1.89
LiveIntervals.cpp updated: 1.48 -> 1.49
---
Log message:
Remove getAllocatedRegNum(). Use getReg() instead.
---
Diffs of the changes: (+22 -22)
Index: llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
diff -u llvm/lib/CodeGen/TwoAddressInstructionPass.cpp:1.14 llvm/lib/CodeGen/TwoAddressInstructionPass.cpp:1.15
--- llvm/lib/CodeGen/TwoAddressInstructionPass.cpp:1.14 Wed Feb 11 20:27:10 2004
+++ llvm/lib/CodeGen/TwoAddressInstructionPass.cpp Fri Feb 13 15:01:20 2004
@@ -97,14 +97,14 @@
DEBUG(std::cerr << "\tinstruction: "; mi->print(std::cerr, TM));
assert(mi->getOperand(1).isRegister() &&
- mi->getOperand(1).getAllocatedRegNum() &&
+ mi->getOperand(1).getReg() &&
mi->getOperand(1).isUse() &&
"two address instruction invalid");
// if the two operands are the same we just remove the use
// and mark the def as def&use
- if (mi->getOperand(0).getAllocatedRegNum() ==
- mi->getOperand(1).getAllocatedRegNum()) {
+ if (mi->getOperand(0).getReg() ==
+ mi->getOperand(1).getReg()) {
}
else {
MadeChange = true;
@@ -114,8 +114,8 @@
// to:
// a = b
// a = a op c
- unsigned regA = mi->getOperand(0).getAllocatedRegNum();
- unsigned regB = mi->getOperand(1).getAllocatedRegNum();
+ unsigned regA = mi->getOperand(0).getReg();
+ unsigned regB = mi->getOperand(1).getReg();
assert(MRegisterInfo::isVirtualRegister(regA) &&
MRegisterInfo::isVirtualRegister(regB) &&
@@ -127,7 +127,7 @@
// because we are in SSA form.
for (unsigned i = 1; i != mi->getNumOperands(); ++i)
assert(!mi->getOperand(i).isRegister() ||
- mi->getOperand(i).getAllocatedRegNum() != (int)regA);
+ mi->getOperand(i).getReg() != regA);
const TargetRegisterClass* rc =
MF.getSSARegMap()->getRegClass(regA);
Index: llvm/lib/CodeGen/RegAllocSimple.cpp
diff -u llvm/lib/CodeGen/RegAllocSimple.cpp:1.49 llvm/lib/CodeGen/RegAllocSimple.cpp:1.50
--- llvm/lib/CodeGen/RegAllocSimple.cpp:1.49 Wed Feb 11 20:27:10 2004
+++ llvm/lib/CodeGen/RegAllocSimple.cpp Fri Feb 13 15:01:20 2004
@@ -173,7 +173,7 @@
MachineOperand &op = MI->getOperand(i);
if (op.isRegister() && MRegisterInfo::isVirtualRegister(op.getReg())) {
- unsigned virtualReg = (unsigned) op.getAllocatedRegNum();
+ unsigned virtualReg = (unsigned) op.getReg();
DEBUG(std::cerr << "op: " << op << "\n");
DEBUG(std::cerr << "\t inst[" << i << "]: ";
MI->print(std::cerr, *TM));
@@ -187,11 +187,11 @@
// must be same register number as the first operand
// This maps a = b + c into b += c, and saves b into a's spot
assert(MI->getOperand(1).isRegister() &&
- MI->getOperand(1).getAllocatedRegNum() &&
+ MI->getOperand(1).getReg() &&
MI->getOperand(1).isUse() &&
"Two address instruction invalid!");
- physReg = MI->getOperand(1).getAllocatedRegNum();
+ physReg = MI->getOperand(1).getReg();
} else {
physReg = getFreeReg(virtualReg);
}
@@ -205,7 +205,7 @@
}
MI->SetMachineOperandReg(i, physReg);
DEBUG(std::cerr << "virt: " << virtualReg <<
- ", phys: " << op.getAllocatedRegNum() << "\n");
+ ", phys: " << op.getReg() << "\n");
}
}
RegClassIdx.clear();
Index: llvm/lib/CodeGen/RegAllocLocal.cpp
diff -u llvm/lib/CodeGen/RegAllocLocal.cpp:1.44 llvm/lib/CodeGen/RegAllocLocal.cpp:1.45
--- llvm/lib/CodeGen/RegAllocLocal.cpp:1.44 Fri Feb 13 12:20:47 2004
+++ llvm/lib/CodeGen/RegAllocLocal.cpp Fri Feb 13 15:01:20 2004
@@ -517,7 +517,7 @@
if (MI->getOperand(i).isUse() &&
!MI->getOperand(i).isDef() && MI->getOperand(i).isRegister() &&
MRegisterInfo::isVirtualRegister(MI->getOperand(i).getReg())) {
- unsigned VirtSrcReg = MI->getOperand(i).getAllocatedRegNum();
+ unsigned VirtSrcReg = MI->getOperand(i).getReg();
unsigned PhysSrcReg = reloadVirtReg(MBB, MI, VirtSrcReg);
MI->SetMachineOperandReg(i, PhysSrcReg); // Assign the input register
}
@@ -551,7 +551,7 @@
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i)
if (MI->getOperand(i).isDef() && MI->getOperand(i).isRegister() &&
MRegisterInfo::isPhysicalRegister(MI->getOperand(i).getReg())) {
- unsigned Reg = MI->getOperand(i).getAllocatedRegNum();
+ unsigned Reg = MI->getOperand(i).getReg();
spillPhysReg(MBB, MI, Reg, true); // Spill any existing value in the reg
PhysRegsUsed[Reg] = 0; // It is free and reserved now
PhysRegsUseOrder.push_back(Reg);
@@ -584,7 +584,7 @@
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i)
if (MI->getOperand(i).isDef() && MI->getOperand(i).isRegister() &&
MRegisterInfo::isVirtualRegister(MI->getOperand(i).getReg())) {
- unsigned DestVirtReg = MI->getOperand(i).getAllocatedRegNum();
+ unsigned DestVirtReg = MI->getOperand(i).getReg();
unsigned DestPhysReg;
// If DestVirtReg already has a value, use it.
Index: llvm/lib/CodeGen/RegAllocLinearScan.cpp
diff -u llvm/lib/CodeGen/RegAllocLinearScan.cpp:1.45 llvm/lib/CodeGen/RegAllocLinearScan.cpp:1.46
--- llvm/lib/CodeGen/RegAllocLinearScan.cpp:1.45 Wed Feb 11 20:27:10 2004
+++ llvm/lib/CodeGen/RegAllocLinearScan.cpp Fri Feb 13 15:01:20 2004
@@ -443,7 +443,7 @@
MachineOperand& op = currentInstr_->getOperand(i);
if (op.isRegister() && op.isUse() &&
MRegisterInfo::isVirtualRegister(op.getReg())) {
- unsigned virtReg = op.getAllocatedRegNum();
+ unsigned virtReg = op.getReg();
unsigned physReg = 0;
Virt2PhysMap::iterator it = v2pMap_.find(virtReg);
if (it != v2pMap_.end()) {
Index: llvm/lib/CodeGen/PHIElimination.cpp
diff -u llvm/lib/CodeGen/PHIElimination.cpp:1.16 llvm/lib/CodeGen/PHIElimination.cpp:1.17
--- llvm/lib/CodeGen/PHIElimination.cpp:1.16 Wed Feb 11 20:27:10 2004
+++ llvm/lib/CodeGen/PHIElimination.cpp Fri Feb 13 15:01:20 2004
@@ -76,7 +76,7 @@
assert(MRegisterInfo::isVirtualRegister(MI->getOperand(0).getReg()) &&
"PHI node doesn't write virt reg?");
- unsigned DestReg = MI->getOperand(0).getAllocatedRegNum();
+ unsigned DestReg = MI->getOperand(0).getReg();
// Create a new register for the incoming PHI arguments
const TargetRegisterClass *RC = MF.getSSARegMap()->getRegClass(DestReg);
Index: llvm/lib/CodeGen/MachineInstr.cpp
diff -u llvm/lib/CodeGen/MachineInstr.cpp:1.88 llvm/lib/CodeGen/MachineInstr.cpp:1.89
--- llvm/lib/CodeGen/MachineInstr.cpp:1.88 Thu Feb 12 22:39:32 2004
+++ llvm/lib/CodeGen/MachineInstr.cpp Fri Feb 13 15:01:20 2004
@@ -187,7 +187,7 @@
static inline void OutputReg(std::ostream &os, unsigned RegNo,
const MRegisterInfo *MRI = 0) {
if (MRI) {
- if (RegNo < MRegisterInfo::FirstVirtualRegister)
+ if (MRegisterInfo::isPhysicalRegister(RegNo))
os << "%" << MRI->get(RegNo).Name;
else
os << "%reg" << RegNo;
@@ -219,14 +219,14 @@
OS << "==";
}
if (MO.hasAllocatedReg())
- OutputReg(OS, MO.getAllocatedRegNum(), MRI);
+ OutputReg(OS, MO.getReg(), MRI);
break;
case MachineOperand::MO_CCRegister:
OS << "%ccreg";
OutputValue(OS, MO.getVRegValue());
if (MO.hasAllocatedReg()) {
OS << "==";
- OutputReg(OS, MO.getAllocatedRegNum(), MRI);
+ OutputReg(OS, MO.getReg(), MRI);
}
break;
case MachineOperand::MO_MachineRegister:
@@ -360,7 +360,7 @@
{
case MachineOperand::MO_VirtualRegister:
if (MO.hasAllocatedReg())
- OutputReg(OS, MO.getAllocatedRegNum());
+ OutputReg(OS, MO.getReg());
if (MO.getVRegValue()) {
if (MO.hasAllocatedReg()) OS << "==";
@@ -373,7 +373,7 @@
OutputValue(OS, MO.getVRegValue());
if (MO.hasAllocatedReg()) {
OS << "==";
- OutputReg(OS, MO.getAllocatedRegNum());
+ OutputReg(OS, MO.getReg());
}
break;
case MachineOperand::MO_MachineRegister:
Index: llvm/lib/CodeGen/LiveIntervals.cpp
diff -u llvm/lib/CodeGen/LiveIntervals.cpp:1.48 llvm/lib/CodeGen/LiveIntervals.cpp:1.49
--- llvm/lib/CodeGen/LiveIntervals.cpp:1.48 Wed Feb 11 20:27:10 2004
+++ llvm/lib/CodeGen/LiveIntervals.cpp Fri Feb 13 15:01:20 2004
@@ -115,7 +115,7 @@
const MachineOperand& mop = mi->getOperand(i);
if (mop.isRegister() &&
MRegisterInfo::isVirtualRegister(mop.getReg())) {
- unsigned reg = mop.getAllocatedRegNum();
+ unsigned reg = mop.getReg();
Reg2IntervalMap::iterator r2iit = r2iMap_.find(reg);
assert(r2iit != r2iMap_.end());
r2iit->second->weight += pow(10.0F, loopDepth);
@@ -313,7 +313,7 @@
MachineOperand& mop = mi->getOperand(i);
// handle register defs - build intervals
if (mop.isRegister() && mop.isDef())
- handleRegisterDef(mbb, mi, mop.getAllocatedRegNum());
+ handleRegisterDef(mbb, mi, mop.getReg());
}
}
}
More information about the llvm-commits
mailing list