[llvm-commits] CVS: llvm/lib/Target/Sparc/RegAlloc/LiveRangeInfo.cpp PhyRegAlloc.cpp
Brian Gaeke
gaeke at cs.uiuc.edu
Wed Feb 11 14:48:08 PST 2004
Changes in directory llvm/lib/Target/Sparc/RegAlloc:
LiveRangeInfo.cpp updated: 1.48 -> 1.49
PhyRegAlloc.cpp updated: 1.132 -> 1.133
---
Log message:
MachineInstr::getOpCode() --> getOpcode() in SPARC back-end.
---
Diffs of the changes: (+18 -18)
Index: llvm/lib/Target/Sparc/RegAlloc/LiveRangeInfo.cpp
diff -u llvm/lib/Target/Sparc/RegAlloc/LiveRangeInfo.cpp:1.48 llvm/lib/Target/Sparc/RegAlloc/LiveRangeInfo.cpp:1.49
--- llvm/lib/Target/Sparc/RegAlloc/LiveRangeInfo.cpp:1.48 Sun Dec 14 07:24:15 2003
+++ llvm/lib/Target/Sparc/RegAlloc/LiveRangeInfo.cpp Wed Feb 11 14:47:34 2004
@@ -176,8 +176,8 @@
// If the machine instruction is a call/return instruction, add it to
// CallRetInstrList for processing its args, ret value, and ret addr.
//
- if(TM.getInstrInfo().isReturn(MInst->getOpCode()) ||
- TM.getInstrInfo().isCall(MInst->getOpCode()))
+ if(TM.getInstrInfo().isReturn(MInst->getOpcode()) ||
+ TM.getInstrInfo().isCall(MInst->getOpcode()))
CallRetInstrList.push_back(MInst);
// iterate over explicit MI operands and create a new LR
@@ -243,7 +243,7 @@
std::vector<MachineInstr*>::iterator It = CallRetInstrList.begin();
for( ; It != CallRetInstrList.end(); ++It) {
MachineInstr *MInst = *It;
- MachineOpCode OpCode = MInst->getOpCode();
+ MachineOpCode OpCode = MInst->getOpcode();
if ((TM.getInstrInfo()).isReturn(OpCode))
MRI.suggestReg4RetValue(MInst, *this);
Index: llvm/lib/Target/Sparc/RegAlloc/PhyRegAlloc.cpp
diff -u llvm/lib/Target/Sparc/RegAlloc/PhyRegAlloc.cpp:1.132 llvm/lib/Target/Sparc/RegAlloc/PhyRegAlloc.cpp:1.133
--- llvm/lib/Target/Sparc/RegAlloc/PhyRegAlloc.cpp:1.132 Wed Jan 28 13:05:43 2004
+++ llvm/lib/Target/Sparc/RegAlloc/PhyRegAlloc.cpp Wed Feb 11 14:47:34 2004
@@ -237,7 +237,7 @@
// get the LV set after the instruction
const ValueSet &LVSetAI = LVI->getLiveVarSetAfterMInst(MInst, BB);
- bool isCallInst = TM.getInstrInfo().isCall(MInst->getOpCode());
+ bool isCallInst = TM.getInstrInfo().isCall(MInst->getOpcode());
if (isCallInst) {
// set the isCallInterference flag of each live range which extends
@@ -262,7 +262,7 @@
// another. This must be done because pseudo-instructions may be
// expanded to multiple instructions by the assembler, so all the
// operands must get distinct registers.
- if (TM.getInstrInfo().isPseudoInstr(MInst->getOpCode()))
+ if (TM.getInstrInfo().isPseudoInstr(MInst->getOpcode()))
addInterf4PseudoInstr(MInst);
// Also add interference for any implicit definitions in a machine
@@ -443,7 +443,7 @@
void PhyRegAlloc::updateInstruction(MachineBasicBlock::iterator& MII,
MachineBasicBlock &MBB) {
MachineInstr* MInst = *MII;
- unsigned Opcode = MInst->getOpCode();
+ unsigned Opcode = MInst->getOpcode();
// Reset tmp stack positions so they can be reused for each machine instr.
MF->getInfo()->popAllTempValues();
@@ -506,7 +506,7 @@
// their assigned registers or insert spill code, as appropriate.
// Also, fix operands of call/return instructions.
for (MachineBasicBlock::iterator MII = MBB.begin(); MII != MBB.end(); ++MII)
- if (! TM.getInstrInfo().isDummyPhiInstr((*MII)->getOpCode()))
+ if (! TM.getInstrInfo().isDummyPhiInstr((*MII)->getOpcode()))
updateInstruction(MII, MBB);
// Now, move code out of delay slots of branches and returns if needed.
@@ -526,14 +526,14 @@
for (MachineBasicBlock::iterator MII = MBB.begin();
MII != MBB.end(); ++MII)
if (unsigned delaySlots =
- TM.getInstrInfo().getNumDelaySlots((*MII)->getOpCode())) {
+ TM.getInstrInfo().getNumDelaySlots((*MII)->getOpcode())) {
MachineInstr *MInst = *MII, *DelaySlotMI = *(MII+1);
// Check the 2 conditions above:
// (1) Does a branch need instructions added after it?
// (2) O/w does delay slot instr. need instrns before or after?
- bool isBranch = (TM.getInstrInfo().isBranch(MInst->getOpCode()) ||
- TM.getInstrInfo().isReturn(MInst->getOpCode()));
+ bool isBranch = (TM.getInstrInfo().isBranch(MInst->getOpcode()) ||
+ TM.getInstrInfo().isReturn(MInst->getOpcode()));
bool cond1 = (isBranch &&
AddedInstrMap.count(MInst) &&
AddedInstrMap[MInst].InstrnsAfter.size() > 0);
@@ -575,7 +575,7 @@
MachineInstr *MInst = *MII;
// do not process Phis
- if (TM.getInstrInfo().isDummyPhiInstr(MInst->getOpCode()))
+ if (TM.getInstrInfo().isDummyPhiInstr(MInst->getOpcode()))
continue;
// if there are any added instructions...
@@ -583,11 +583,11 @@
AddedInstrns &CallAI = AddedInstrMap[MInst];
#ifndef NDEBUG
- bool isBranch = (TM.getInstrInfo().isBranch(MInst->getOpCode()) ||
- TM.getInstrInfo().isReturn(MInst->getOpCode()));
+ bool isBranch = (TM.getInstrInfo().isBranch(MInst->getOpcode()) ||
+ TM.getInstrInfo().isReturn(MInst->getOpcode()));
assert((!isBranch ||
AddedInstrMap[MInst].InstrnsAfter.size() <=
- TM.getInstrInfo().getNumDelaySlots(MInst->getOpCode())) &&
+ TM.getInstrInfo().getNumDelaySlots(MInst->getOpcode())) &&
"Cannot put more than #delaySlots instrns after "
"branch or return! Need to handle temps differently.");
#endif
@@ -638,9 +638,9 @@
MachineInstr *MInst = *MII;
const BasicBlock *BB = MBB.getBasicBlock();
- assert((! TM.getInstrInfo().isCall(MInst->getOpCode()) || OpNum == 0) &&
+ assert((! TM.getInstrInfo().isCall(MInst->getOpcode()) || OpNum == 0) &&
"Outgoing arg of a call must be handled elsewhere (func arg ok)");
- assert(! TM.getInstrInfo().isReturn(MInst->getOpCode()) &&
+ assert(! TM.getInstrInfo().isReturn(MInst->getOpcode()) &&
"Return value of a ret must be handled elsewhere");
MachineOperand& Op = MInst->getOperand(OpNum);
@@ -659,7 +659,7 @@
// trample those! Verify that the set is included in the LV set before MInst.
if (MII != MBB.begin()) {
MachineInstr *PredMI = *(MII-1);
- if (unsigned DS = TM.getInstrInfo().getNumDelaySlots(PredMI->getOpCode()))
+ if (unsigned DS = TM.getInstrInfo().getNumDelaySlots(PredMI->getOpcode()))
assert(set_difference(LVI->getLiveVarSetBeforeMInst(PredMI), LVSetBef)
.empty() && "Live-var set before branch should be included in "
"live-var set of each delay slot instruction!");
@@ -745,7 +745,7 @@
std::vector<MachineInstr*> &instrnsAfter,
MachineInstr *CallMI,
const BasicBlock *BB) {
- assert(TM.getInstrInfo().isCall(CallMI->getOpCode()));
+ assert(TM.getInstrInfo().isCall(CallMI->getOpcode()));
// hash set to record which registers were saved/restored
hash_set<unsigned> PushedRegSet;
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