[llvm-commits] CVS: llvm/lib/Target/Sparc/LiveVar/BBLiveVar.cpp FunctionLiveVarInfo.cpp

[Brian Gaeke]

Changes in directory llvm/lib/Target/Sparc/LiveVar:

BBLiveVar.cpp updated: 1.42 -> 1.43
FunctionLiveVarInfo.cpp updated: 1.51 -> 1.52

---
Log message:

MachineInstr::getOpCode() --> getOpcode() in SPARC back-end.

---
Diffs of the changes:  (+4 -4)

Index: llvm/lib/Target/Sparc/LiveVar/BBLiveVar.cpp
diff -u llvm/lib/Target/Sparc/LiveVar/BBLiveVar.cpp:1.42 llvm/lib/Target/Sparc/LiveVar/BBLiveVar.cpp:1.43
--- llvm/lib/Target/Sparc/LiveVar/BBLiveVar.cpp:1.42	Wed Feb 11 11:55:09 2004
+++ llvm/lib/Target/Sparc/LiveVar/BBLiveVar.cpp	Wed Feb 11 14:47:34 2004
@@ -78,7 +78,7 @@
         // Put Phi operands in UseSet for the incoming edge, not node.
         // They must not "hide" later defs, and must be handled specially
         // during set propagation over the CFG.
-	if (MI->getOpCode() == V9::PHI) {         // for a phi node
+	if (MI->getOpcode() == V9::PHI) {         // for a phi node
           const Value *ArgVal = Op;
 	  const BasicBlock *PredBB = cast<BasicBlock>(*++OpI); // next ptr is BB
 	  
@@ -97,7 +97,7 @@
 
     // do for implicit operands as well
     for (unsigned i = 0; i < MI->getNumImplicitRefs(); ++i) {
-      assert(MI->getOpCode() != V9::PHI && "Phi cannot have implicit operands");
+      assert(MI->getOpcode() != V9::PHI && "Phi cannot have implicit operands");
       const Value *Op = MI->getImplicitRef(i);
 
       if (Op->getType() == Type::LabelTy)             // don't process labels


Index: llvm/lib/Target/Sparc/LiveVar/FunctionLiveVarInfo.cpp
diff -u llvm/lib/Target/Sparc/LiveVar/FunctionLiveVarInfo.cpp:1.51 llvm/lib/Target/Sparc/LiveVar/FunctionLiveVarInfo.cpp:1.52
--- llvm/lib/Target/Sparc/LiveVar/FunctionLiveVarInfo.cpp:1.51	Sun Dec 14 07:24:17 2003
+++ llvm/lib/Target/Sparc/LiveVar/FunctionLiveVarInfo.cpp	Wed Feb 11 14:47:34 2004
@@ -295,12 +295,12 @@
     // If the current machine instruction has delay slots, mark values
     // used by this instruction as live before and after each delay slot
     // instruction (After(MI) is the same as Before(MI+1) except for last MI).
-    if (unsigned DS = TM.getInstrInfo().getNumDelaySlots(MI->getOpCode())) {
+    if (unsigned DS = TM.getInstrInfo().getNumDelaySlots(MI->getOpcode())) {
       MachineBasicBlock::const_iterator fwdMII = MII.base(); // ptr to *next* MI
       for (unsigned i = 0; i < DS; ++i, ++fwdMII) {
         assert(fwdMII != MIVec.end() && "Missing instruction in delay slot?");
         MachineInstr* DelaySlotMI = *fwdMII;
-        if (! TM.getInstrInfo().isNop(DelaySlotMI->getOpCode())) {
+        if (! TM.getInstrInfo().isNop(DelaySlotMI->getOpcode())) {
           set_union(*MInst2LVSetBI[DelaySlotMI], *NewSet);
           if (i+1 == DS)
             set_union(*MInst2LVSetAI[DelaySlotMI], *NewSet);