[llvm-commits] CVS: llvm/lib/Target/X86/InstSelectSimple.cpp

[Brian Gaeke]

Changes in directory llvm/lib/Target/X86:

InstSelectSimple.cpp updated: 1.140 -> 1.141

---
Log message:

Stub for constant shift expr support.


---
Diffs of the changes:  (+23 -0)

Index: llvm/lib/Target/X86/InstSelectSimple.cpp
diff -u llvm/lib/Target/X86/InstSelectSimple.cpp:1.140 llvm/lib/Target/X86/InstSelectSimple.cpp:1.141
--- llvm/lib/Target/X86/InstSelectSimple.cpp:1.140	Tue Nov 18 11:47:05 2003
+++ llvm/lib/Target/X86/InstSelectSimple.cpp	Fri Nov 21 23:18:35 2003
@@ -224,6 +224,13 @@
                             MachineBasicBlock::iterator &IP,
                             Value *Op0, Value *Op1, unsigned Opcode,
                             unsigned TargetReg);
+
+    /// emitShiftOperation - Common code shared between visitShiftInst and
+    /// constant expression support.
+    void emitShiftOperation(MachineBasicBlock *BB,
+                            MachineBasicBlock::iterator &IP,
+                            Value *Op0, Value *Op1, unsigned Opcode,
+                            unsigned TargetReg);
  
 
     /// copyConstantToRegister - Output the instructions required to put the
@@ -384,6 +391,12 @@
                          CE->getOpcode(), R);
       return;
 
+    case Instruction::Shl:
+    case Instruction::Shr:
+      emitShiftOperation(MBB, IP, CE->getOperand(0), CE->getOperand(1),
+                         CE->getOpcode(), R);
+      break;
+
     default:
       std::cerr << "Offending expr: " << C << "\n";
       assert(0 && "Constant expression not yet handled!\n");
@@ -1566,6 +1579,16 @@
     const unsigned *Opc = NonConstantOperand[isLeftShift*2+isSigned];
     BuildMI(BB, Opc[Class], 1, DestReg).addReg(SrcReg);
   }
+}
+
+/// emitShiftOperation - Common code shared between visitShiftInst and
+/// constant expression support.
+void ISel::emitShiftOperation(MachineBasicBlock *MBB,
+                              MachineBasicBlock::iterator &IP,
+                              Value *Op0, Value *Op1, unsigned Opcode,
+                              unsigned TargetReg) {
+  // FIXME: Should do all the stuff from visitShiftInst, but use BMI
+  assert (0 && "Constant shift operations not yet handled");
 }