[llvm-commits] CVS: llvm/lib/Target/X86/InstSelectSimple.cpp

[Chris Lattner]

Changes in directory llvm/lib/Target/X86:

InstSelectSimple.cpp updated: 1.139 -> 1.140

---
Log message:

Fix PR123


---
Diffs of the changes:  (+7 -7)

Index: llvm/lib/Target/X86/InstSelectSimple.cpp
diff -u llvm/lib/Target/X86/InstSelectSimple.cpp:1.139 llvm/lib/Target/X86/InstSelectSimple.cpp:1.140
--- llvm/lib/Target/X86/InstSelectSimple.cpp:1.139	Tue Nov 11 16:41:33 2003
+++ llvm/lib/Target/X86/InstSelectSimple.cpp	Tue Nov 18 11:47:05 2003
@@ -1375,7 +1375,7 @@
   switch (Class) {
   case cFP:              // Floating point divide
     if (isDiv) {
-      BuildMI(BB, X86::FpDIV, 2, ResultReg).addReg(Op0Reg).addReg(Op1Reg);
+      BMI(BB, IP, X86::FpDIV, 2, ResultReg).addReg(Op0Reg).addReg(Op1Reg);
     } else {               // Floating point remainder...
       MachineInstr *TheCall =
         BuildMI(X86::CALLpcrel32, 1).addExternalSymbol("fmod", true);
@@ -1420,26 +1420,26 @@
   unsigned ExtReg = ExtRegs[Class];
 
   // Put the first operand into one of the A registers...
-  BuildMI(BB, MovOpcode[Class], 1, Reg).addReg(Op0Reg);
+  BMI(BB, IP, MovOpcode[Class], 1, Reg).addReg(Op0Reg);
 
   if (isSigned) {
     // Emit a sign extension instruction...
     unsigned ShiftResult = makeAnotherReg(Ty);
-    BuildMI(BB, SarOpcode[Class], 2, ShiftResult).addReg(Op0Reg).addZImm(31);
-    BuildMI(BB, MovOpcode[Class], 1, ExtReg).addReg(ShiftResult);
+    BMI(BB, IP, SarOpcode[Class], 2, ShiftResult).addReg(Op0Reg).addZImm(31);
+    BMI(BB, IP, MovOpcode[Class], 1, ExtReg).addReg(ShiftResult);
   } else {
     // If unsigned, emit a zeroing instruction... (reg = xor reg, reg)
-    BuildMI(BB, ClrOpcode[Class], 2, ExtReg).addReg(ExtReg).addReg(ExtReg);
+    BMI(BB, IP, ClrOpcode[Class], 2, ExtReg).addReg(ExtReg).addReg(ExtReg);
   }
 
   // Emit the appropriate divide or remainder instruction...
-  BuildMI(BB, DivOpcode[isSigned][Class], 1).addReg(Op1Reg);
+  BMI(BB, IP, DivOpcode[isSigned][Class], 1).addReg(Op1Reg);
 
   // Figure out which register we want to pick the result out of...
   unsigned DestReg = isDiv ? Reg : ExtReg;
   
   // Put the result into the destination register...
-  BuildMI(BB, MovOpcode[Class], 1, ResultReg).addReg(DestReg);
+  BMI(BB, IP, MovOpcode[Class], 1, ResultReg).addReg(DestReg);
 }