[llvm-commits] CVS: llvm/lib/Target/Sparc/SparcV9_F3.td SparcV9.td

[Misha Brukman]

Changes in directory llvm/lib/Target/Sparc:

SparcV9_F3.td updated: 1.7 -> 1.8
SparcV9.td updated: 1.11 -> 1.12

---
Log message:

Store instructions are different from other Format 3.1/3.2 instructions in that
they prefer the destination register to be last. Thus, two new classes were made
for them that accomodate for having this layout of operands (F3_1rd, F3_2rd).


---
Diffs of the changes:

Index: llvm/lib/Target/Sparc/SparcV9_F3.td
diff -u llvm/lib/Target/Sparc/SparcV9_F3.td:1.7 llvm/lib/Target/Sparc/SparcV9_F3.td:1.8
--- llvm/lib/Target/Sparc/SparcV9_F3.td:1.7	Mon Jun  2 20:11:58 2003
+++ llvm/lib/Target/Sparc/SparcV9_F3.td	Mon Jun  2 22:20:14 2003
@@ -62,12 +62,31 @@
   set Inst{29-25} = rd;
 }
 
-// F3_rd - Common class of instructions that only have an rd field
+// F3_rd - Common class of instructions that have an rd field
 class F3_rd : F3 {
   bits<5> rd;
   set Inst{29-25} = rd;
 }
 
+// F3_rdrs1 - Common class of instructions that have rd and rs1 fields
+class F3_rdrs1 : F3_rd {
+  bits<5> rs1;
+  set Inst{18-14} = rs1;
+}
+
+// F3_rdrs1simm13 - Common class of instructions that have rd, rs1, and simm13
+class F3_rdrs1simm13 : F3_rd {
+  bits<13> simm13;
+  set Inst{12-0} = simm13;
+}
+
+
+// F3_rdrs1rs2 - Common class of instructions that have rd, rs1, and rs2 fields
+class F3_rdrs1rs2 : F3_rs1 {
+  bits<5> rs2;
+  set Inst{4-0} = rs2;
+}
+
 
 // Specific F3 classes...
 //
@@ -80,7 +99,24 @@
   //set Inst{12-5} = dontcare;
 }
 
+// The store instructions seem to like to see rd first, then rs1 and rs2
+class F3_1rd<bits<2> opVal, bits<6> op3val, string name> : F3_rdrs1rs2 {
+  set op  = opVal;
+  set op3 = op3val;
+  set Name = name;
+  set Inst{13} = 0;   // i field = 0
+  //set Inst{12-5} = dontcare;
+}
+
 class F3_2<bits<2> opVal, bits<6> op3val, string name> : F3_rs1simm13rd {
+  set op  = opVal;
+  set op3 = op3val;
+  set Name = name;
+  set Inst{13} = 1;   // i field = 1
+}
+
+// The store instructions seem to like to see rd first, then rs1 and imm
+class F3_2rd<bits<2> opVal, bits<6> op3val, string name> : F3_rdrs1simm13 {
   set op  = opVal;
   set op3 = op3val;
   set Name = name;


Index: llvm/lib/Target/Sparc/SparcV9.td
diff -u llvm/lib/Target/Sparc/SparcV9.td:1.11 llvm/lib/Target/Sparc/SparcV9.td:1.12
--- llvm/lib/Target/Sparc/SparcV9.td:1.11	Mon Jun  2 20:16:27 2003
+++ llvm/lib/Target/Sparc/SparcV9.td	Mon Jun  2 22:20:14 2003
@@ -603,15 +603,15 @@
 // Not currently used in the Sparc backend
 
 // Section A.52: Store Floating-point -p225
-def STFr  : F3_1<3, 0b100100, "st">;                      // st r, [r+r]
-def STFi  : F3_2<3, 0b100100, "st">;                      // st r, [r+i]
-def STDFr : F3_1<3, 0b100111, "std">;                     // std r, [r+r]
-def STDFi : F3_2<3, 0b100111, "std">;                     // std r, [r+i]
+def STFr  : F3_1rd<3, 0b100100, "st">;                      // st r, [r+r]
+def STFi  : F3_2rd<3, 0b100100, "st">;                      // st r, [r+i]
+def STDFr : F3_1rd<3, 0b100111, "std">;                     // std r, [r+r]
+def STDFi : F3_2rd<3, 0b100111, "std">;                     // std r, [r+i]
 
 // Not currently used in the Sparc backend
 #if 0
-def STQFr : F3_1<3, 0b100110, "stq">;                     // stq r, [r+r]
-def STQFi : F3_2<3, 0b100110, "stq">;                     // stq r, [r+i]
+def STQFr : F3_1rd<3, 0b100110, "stq">;                     // stq r, [r+r]
+def STQFi : F3_2rd<3, 0b100110, "stq">;                     // stq r, [r+i]
 #endif
 
 set isDeprecated = 1 in {