[llvm-commits] CVS: llvm/include/llvm/Reoptimizer/BinInterface/sparcpriv.h

[Anand Shukla]

Changes in directory llvm/include/llvm/Reoptimizer/BinInterface:

sparcpriv.h added (r1.1)

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Log message:

First version of working bininterface API/implementation

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Diffs of the changes:

Index: llvm/include/llvm/Reoptimizer/BinInterface/sparcpriv.h
diff -c /dev/null llvm/include/llvm/Reoptimizer/BinInterface/sparcpriv.h:1.1
*** /dev/null	Sat May 31 17:19:13 2003
--- llvm/include/llvm/Reoptimizer/BinInterface/sparcpriv.h	Sat May 31 17:19:03 2003
***************
*** 0 ****
--- 1,118 ----
+ //===--------llvm/Reoptimizer/BinInterface/sparcpriv.h------------*- C++ -*--=//
+ //
+ // BinInterface private structures and constants
+ //
+ //===----------------------------------------------------------------------===//
+ 
+ #ifndef __SPARC_PRIV_H__
+ #define __SPARC_PRIV_H__
+ 
+ #include <vector>
+ using std::vector;
+ 
+ //
+ //  Instruction flag definitions
+ //
+ #define IF_ALUOP        (IF_USR << 1)  // generic ALU
+ #define IF_PHI          (IF_USR << 2)  // phi node
+ #define IF_NODELIVEIN   (IF_USR << 3)  // instr field is register to bind to
+ #define IF_REGSHUFFLE   (IF_USR << 5)  // register shuffle (calls and liveouts)
+ #define IF_BRINTERNAL   (IF_USR << 6)  // is this an INTERNAL branch 
+ #define IF_LIVEOUT      (IF_USR << 7)  // this instruction is liveout?
+ 
+ 
+ 
+ // a call instruction will spill all the outgoing registers O0->O7 (R8-R15)
+ #define R_CALLSPILLS  0x0000FF00
+ 
+ 
+ // a mask of registers that if a trace
+ // reads/writes to we IGNORE dataflow
+ // implications (stack register and null register)
+ #define RM_IGNORE ((1 << R_SP) | 1 | (1 << R_BP))
+ 
+ // allocate all regs except R0(G0), O6(R14)(SP), I6(FP), g1-g7
+ #define R_ALLOCREGS   (0xFFFFFFFF & ~ RM_IGNORE  & ~(0xff))       
+ 
+ 
+ // Max of 62 epilogs (64 sections in all)
+ #define MAX_SECTIONS 64
+ 
+ struct vreginfo
+ {
+    unsigned uses;       // number of times virtual register is referenced
+    unsigned lastuse;    // latest use
+    int      mreg;       // mreg mapped to (use VREG_ISMEM/VREG_ISREG)
+ };
+ 
+ 
+ // This is the data passed back from the register allocator
+ struct regalloc
+ {
+    vector<unsigned>  ssa_to_vreg;  // map of SSA Id's to virtual registers
+    vector<vreginfo>  vregs;        // virtual register descriptors
+    int                spillreg;
+    int                memspills[32];
+    unsigned           touched_regs;
+    unsigned           stack_size;
+    unsigned           liveout_regs;
+    unsigned           livein_regs;
+ 
+   //regalloc(Allocator * alloc){}
+   regalloc(){}
+   //    : ssa_to_vreg(alloc), vregs(alloc) {}
+ };
+ 
+ struct shufflepair
+ {
+   int reg;   //Physical register
+   int gen;  // SSAid of instruction producing the register
+   shufflepair() {}
+   shufflepair(int r, int g) : reg(r), gen(g) {}
+ };
+ 
+ struct instruction{
+   unsigned next;
+   unsigned prev;
+   unsigned self;
+   unsigned flags;
+   bool isFloatingPoint; //This should go away once floating point is
+   //fully implemented
+   unsigned instr;
+   union
+   {
+     struct
+     {
+       unsigned genrs1;
+       unsigned genrs2;
+       unsigned genccf;
+       unsigned genrd;  //wonderful SUN.. we can read from RD (STX)
+     } alu;
+     struct
+     {
+       unsigned genrs1;
+       unsigned dest;      // id # of destination section
+     } ibranch;  // internal branch
+     struct
+     {
+       unsigned genrs1;
+       unsigned * dest;
+     } ebranch;  // external branch
+     struct
+     {
+       vector<unsigned> * params;
+     }phi;
+     struct
+     {
+       unsigned reg;
+     } livein;
+     struct
+     {
+       vector<shufflepair> * shuffles;
+     } regshuffle;
+   };
+ };
+ 
+ #endif
+ 
+