[llvm-commits] CVS: llvm/include/llvm/Reoptimizer/BinInterface/sparcbin.h

Anand Shukla ashukla at cs.uiuc.edu
Sat May 31 17:19:11 PDT 2003


Changes in directory llvm/include/llvm/Reoptimizer/BinInterface:

sparcbin.h added (r1.1)

---
Log message:

First version of working bininterface API/implementation

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Diffs of the changes:

Index: llvm/include/llvm/Reoptimizer/BinInterface/sparcbin.h
diff -c /dev/null llvm/include/llvm/Reoptimizer/BinInterface/sparcbin.h:1.1
*** /dev/null	Sat May 31 17:18:50 2003
--- llvm/include/llvm/Reoptimizer/BinInterface/sparcbin.h	Sat May 31 17:18:40 2003
***************
*** 0 ****
--- 1,275 ----
+ //===--------llvm/Reoptimizer/BinInterface/sparcbin.h-------------*- C++ -*--=//
+ //
+ //  BinInterface: API for runtime manipulation of binary code
+ //
+ //  Notes:
+ /// move_instr into epilog ONLY after reduce()
+ /// Remove instruction from anywhere before reduce()
+ //
+ //===----------------------------------------------------------------------===//
+ 
+ #ifndef __BININTERFACE_H__
+ #define __BININTERFACE_H__
+ 
+ #include "llvm/Reoptimizer/VirtualMem.h"
+ #include "llvm/Reoptimizer/TraceCache.h"
+ #include "llvm/Reoptimizer/InstrUtils.h"
+ #include "analyze.h"
+ #include "sparcpriv.h"
+ #include <map>
+ #include <vector>
+ 
+ using std::vector;
+ 
+ struct vreginfo;
+ struct regmask;
+ struct regmask32;
+ struct instruction;
+ struct regalloc;
+ struct shufflepair;
+ 
+ 
+ static const unsigned SECTION_PROLOG =0;
+ static const unsigned SECTION_TRACE  =1;
+ 
+ class BinInterface
+ {
+    private:
+   
+   //Allocator             *   alloca;   // primary stack allocator
+       vector<instruction *>    itable;   // maps an unsigned ID
+       // to an instruction
+ 
+       vector<unsigned>         sections;
+       vector<unsigned>         livein;   // pointers to all livein nodes
+ 
+       //virtual mem
+       VirtualMem *vm;
+       //TraceCache
+       TraceCache *tr;
+ 
+       //map of [epilog, address where epilog return]
+       std::map<unsigned int, unsigned int *> epToRetAddr;
+ 
+       //vector of pinned down SSA IDs
+       std::vector<unsigned int> pinned;
+ 
+       //vector of liveout regs
+       std::vector<unsigned char> liveOutRegs;
+ 
+       // make SURE instr has already has its SELF index
+       // assigned!
+       void insert_instr(unsigned instr_id, instruction * instr);
+       void push_section();
+ 
+ 
+       // insertions are delayed to facilitate branch analysis
+       struct insertion
+       {
+          unsigned * begin;
+          unsigned * end;
+          unsigned   section;
+          unsigned   idstart;
+       };
+ 
+       void process_branch(const insertion & i, 
+                           unsigned ** brdest, int scns);
+                           
+       void construct_merge(int s, int brdest, unsigned map[32], 
+                            vector<vector<unsigned int> > & regmaps);
+ 
+       void process_section(unsigned s, unsigned map[32],
+                            vector<vector<unsigned int> > & regmaps);
+                            
+       void process_markgen(unsigned s, unsigned map[32]);
+ 
+       void process_marklivein(unsigned s, unsigned map[32]);
+ 
+       void process_liveouts(unsigned int s);
+ 
+       void create_exits_liveouts(vector<vector<unsigned int> > & regmaps);
+ 
+       vector<insertion> queue;
+       instruction * allocphi();
+ 
+       // returns itable index for new live in node
+       unsigned          allocnodelivein(unsigned int s, unsigned int reg);
+       unsigned          allocnodeshuffles(int s, vector<shufflepair> * 
+                                           shuffles);
+ 
+       int               spill_load(int vreg, regmask32 & rmask,
+                                    const int memspills[32],  int & freereg, 
+                                    int spills[3], int & spill_cnt, 
+                                    unsigned * & out);
+                                    
+       void              select(regalloc & regs);
+ 
+       int			    spillreg(int spillloc, unsigned * & out, 
+                                  vector<vreginfo> & vregs, regmask & freeregs,
+                                  unsigned hwregs[32]);
+ 
+ 
+       void              prepare_exit(const regalloc & regalloc, 
+                                      vector<shufflepair> * mod,  
+                                      unsigned * & out);
+                                      
+       unsigned          emit_gen(unsigned char * out, const regalloc & regs);
+ 
+ 
+    public:
+ 
+ 
+       // Call newepilog() to get the ID of a new epilog section
+       unsigned     newepilog();
+       // IDs of prolog and trace sections
+ 
+       // initial instruction block insertion.  specify section number
+       // and iterator to machine instructions
+       // (iend is the first instruction not to insert)
+       unsigned  insert(unsigned section, unsigned *ibegin, unsigned * iend);
+ 
+       //get the FIRST instruction in this section
+       //The first instruction is always a dummy instruction
+       unsigned int first(unsigned sectionId){
+ 	assert(sections.size() > sectionId);
+ 	return sections[sectionId];
+       }
+ 
+       //  Returns the ID of the first instruction in the section
+       unsigned  begin(unsigned sectionid) 
+         { return (itable[sections[sectionid]])->next; }
+       //  Returns the ID to stop iterating on (header node)
+       unsigned  end  (unsigned sectionid) 
+         { return sections[sectionid]; }
+ 
+       // Find predecessor/sucessor of instructions
+       unsigned  next(unsigned t) 
+         { return itable[t]->next; }
+         
+       unsigned  prev(unsigned t) 
+         { return itable[t]->prev; }
+ 
+       // Delete any instruction by instruction ID
+       void remove(unsigned);
+ 
+       // Move instruction id to just after after_this 
+       //IMPORTANR: For newly created instruction that are not yet placed
+       // in any section. For instructions already existing in
+       // any section, use move_instr or move_instr_before
+       void         move(unsigned id, unsigned after_this);
+ 
+       //For an instruction already existing in some section
+       //Move instruction AFTER an instruction id
+       void move_instr(unsigned instr_id, unsigned after_this);
+       
+       //For an instruction already existing in some section
+       //Move instruction BEFORE an instruction id
+       void move_instr_before(unsigned instr_id, unsigned before_this);
+ 
+       //move to end of section
+       void moveToEnd(unsigned instr_id, unsigned section);
+ 
+       // Swap the locations of 2 instructions
+       void         swap(unsigned a, unsigned b);
+ 
+       // Get the opcode associated with a given instruction
+       unsigned     getopcode(unsigned);
+ 
+       // Query to get the RS1/RS2/CC0 generation information. Returns
+       // the instruction it is getting the result from.  Make
+       // SURE the instruction is not a branch or PHI node or else
+       // these results will be gibberish
+       bool hasrs1(unsigned);
+       bool hasrs2(unsigned);
+       unsigned  getrs1(unsigned);
+       unsigned  getrs2(unsigned);
+       unsigned  getcc0(unsigned);
+       
+       //Must be performed AFTER reduce
+       void setrs1(unsigned inst, unsigned setTo);
+       void setrs2(unsigned inst, unsigned setto);
+ 
+ 
+       // Instructions exist outside of any section when created
+       //  you must place them using 'move'!
+ 
+       // New relative branch, destination is an instruction ID (returns
+       // branch instruction ID)
+       unsigned newbranch(unsigned op, unsigned dest);
+ 
+       // New relative branch, destination is a section ID (returns
+       // branch instruction ID)
+       //rs1 is SSAid of register value on which branch condition is determined
+       unsigned newbranch(unsigned op, unsigned rs1, unsigned dest);
+ 
+       // New relative branch, destination is a absolute address (returns
+       // branch instruction ID)
+       // rs1 is SSAid of register value on which branch condition is determined
+       unsigned newabsbranch(unsigned op, unsigned rs1, unsigned *dest);
+ 
+       // New relative branch, destination is a section ID (returns
+       // branch instruction ID)
+       // NO rs1
+       unsigned newabsbranch(unsigned op, unsigned *dest);
+ 
+       //set the branch as internal
+       //dest is the desctination section
+       void setBranchAsInternal(unsigned cid, unsigned dest);
+ 
+       //change the branch destination
+       //should be called ONLY AFTER complete()
+       void BinInterface::setBranchDest(unsigned cid, unsigned int *dest);
+ 
+       //reverse the branch condition
+       void reverseBranch(unsigned cid);
+ 
+       // General operation generation
+       unsigned newalu  (unsigned op, unsigned rs1, unsigned rs2);
+       unsigned newalucc(unsigned op, unsigned rs1, unsigned rs2, unsigned cc0);
+ 
+       //new NOP
+       unsigned newnop();
+ 
+       //assign return add to epilog
+       void assignRetAdress(unsigned int sec, unsigned int *addr);
+ 
+       //pin down a ssaid
+       void pinDown(unsigned int);
+ 
+       // Must be called before any manipulations ->
+       //  this translates the instruction insert with 'insert'
+       //  into SSA form
+ 
+       // The liveout is a mask of registers that are live out
+       // if you want to make it assume all registers are pot
+       // live out -> pass in 0xFFFFFFFE (reg 0 cannot be liveout)
+       void        reduce();
+       void        complete();
+       void        liveout(unsigned live);
+ 
+       //set a given register as liveout
+       //all instructions that write into that register become
+       //liveout
+       void setLiveOutReg(unsigned char rs);
+ 
+       // Predicts size (within a power of 2) of neccesary code
+       // buffer
+       unsigned    predict();
+ 
+       // Emit code into user specified buffer
+       unsigned     emit(unsigned char * out);
+ 
+       // Debug printing
+       void        print();
+       void        print(unsigned scn);
+ 
+       // Use to reset for a second pass (internally stack allocation is used)
+       void        clear();
+       
+       BinInterface(unsigned heapsize);
+       BinInterface(unsigned heapsize, VirtualMem *vmem, TraceCache *trc);
+       ~BinInterface();
+ };
+ #endif
+ 
+ 





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