[llvm-commits] CVS: llvm/lib/CodeGen/InstrSched/InstrScheduling.cpp SchedGraph.cpp

[Chris Lattner]

Changes in directory llvm/lib/CodeGen/InstrSched:

InstrScheduling.cpp updated: 1.49 -> 1.50
SchedGraph.cpp updated: 1.40 -> 1.41

---
Log message:

Rename MachineInstrInfo -> TargetInstrInfo



---
Diffs of the changes:

Index: llvm/lib/CodeGen/InstrSched/InstrScheduling.cpp
diff -u llvm/lib/CodeGen/InstrSched/InstrScheduling.cpp:1.49 llvm/lib/CodeGen/InstrSched/InstrScheduling.cpp:1.50
--- llvm/lib/CodeGen/InstrSched/InstrScheduling.cpp:1.49	Sat Dec 28 21:12:55 2002
+++ llvm/lib/CodeGen/InstrSched/InstrScheduling.cpp	Tue Jan 14 15:58:42 2003
@@ -370,7 +370,7 @@
   // Simplify access to the machine instruction info
   //----------------------------------------------------------------------
   
-  inline const MachineInstrInfo& getInstrInfo	() const {
+  inline const TargetInstrInfo& getInstrInfo	() const {
     return schedInfo.getInstrInfo();
   }
   
@@ -630,7 +630,7 @@
 static void
 RecordSchedule(MachineBasicBlock &MBB, const SchedulingManager& S)
 {
-  const MachineInstrInfo& mii = S.schedInfo.getInstrInfo();
+  const TargetInstrInfo& mii = S.schedInfo.getInstrInfo();
   
 #ifndef NDEBUG
   // Lets make sure we didn't lose any instructions, except possibly
@@ -1075,7 +1075,7 @@
     return false;
   
   // don't put a load-use dependence in the delay slot of a branch
-  const MachineInstrInfo& mii = S.getInstrInfo();
+  const TargetInstrInfo& mii = S.getInstrInfo();
   
   for (SchedGraphNode::const_iterator EI = node->beginInEdges();
        EI != node->endInEdges(); ++EI)
@@ -1143,7 +1143,7 @@
                                     SchedGraphNode* brNode,
                                     vector<SchedGraphNode*>& sdelayNodeVec)
 {
-  const MachineInstrInfo& mii = S.getInstrInfo();
+  const TargetInstrInfo& mii = S.getInstrInfo();
   unsigned ndelays =
     mii.getNumDelaySlots(brNode->getOpCode());
   
@@ -1207,7 +1207,7 @@
                                        SchedGraph* graph)
 {
   vector<SchedGraphNode*> nopNodeVec;   // this will hold unused NOPs
-  const MachineInstrInfo& mii = S.getInstrInfo();
+  const TargetInstrInfo& mii = S.getInstrInfo();
   const MachineInstr* brInstr = node->getMachineInstr();
   unsigned ndelays= mii.getNumDelaySlots(brInstr->getOpCode());
   assert(ndelays > 0 && "Unnecessary call to replace NOPs");
@@ -1283,7 +1283,7 @@
 ChooseInstructionsForDelaySlots(SchedulingManager& S, MachineBasicBlock &MBB,
 				SchedGraph *graph)
 {
-  const MachineInstrInfo& mii = S.getInstrInfo();
+  const TargetInstrInfo& mii = S.getInstrInfo();
 
   Instruction *termInstr = (Instruction*)MBB.getBasicBlock()->getTerminator();
   MachineCodeForInstruction &termMvec=MachineCodeForInstruction::get(termInstr);


Index: llvm/lib/CodeGen/InstrSched/SchedGraph.cpp
diff -u llvm/lib/CodeGen/InstrSched/SchedGraph.cpp:1.40 llvm/lib/CodeGen/InstrSched/SchedGraph.cpp:1.41
--- llvm/lib/CodeGen/InstrSched/SchedGraph.cpp:1.40	Sat Dec 28 21:12:55 2002
+++ llvm/lib/CodeGen/InstrSched/SchedGraph.cpp	Tue Jan 14 15:58:42 2003
@@ -12,7 +12,7 @@
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/Target/TargetRegInfo.h"
 #include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/MachineInstrInfo.h"
+#include "llvm/Target/TargetInstrInfo.h"
 #include "llvm/Function.h"
 #include "llvm/iOther.h"
 #include "Support/StringExtras.h"
@@ -325,7 +325,7 @@
 SchedGraph::addCDEdges(const TerminatorInst* term,
 		       const TargetMachine& target)
 {
-  const MachineInstrInfo& mii = target.getInstrInfo();
+  const TargetInstrInfo& mii = target.getInstrInfo();
   MachineCodeForInstruction &termMvec = MachineCodeForInstruction::get(term);
   
   // Find the first branch instr in the sequence of machine instrs for term
@@ -434,7 +434,7 @@
 SchedGraph::addMemEdges(const vector<SchedGraphNode*>& memNodeVec,
 			const TargetMachine& target)
 {
-  const MachineInstrInfo& mii = target.getInstrInfo();
+  const TargetInstrInfo& mii = target.getInstrInfo();
   
   // Instructions in memNodeVec are in execution order within the basic block,
   // so simply look at all pairs <memNodeVec[i], memNodeVec[j: j > i]>.
@@ -471,7 +471,7 @@
                            MachineBasicBlock& bbMvec,
                            const TargetMachine& target)
 {
-  const MachineInstrInfo& mii = target.getInstrInfo();
+  const TargetInstrInfo& mii = target.getInstrInfo();
   vector<SchedGraphNode*> callNodeVec;
   
   // Find the call instruction nodes and put them in a vector.
@@ -675,7 +675,7 @@
                                   RegToRefVecMap& regToRefVecMap,
                                   ValueToDefVecMap& valueToDefVecMap)
 {
-  const MachineInstrInfo& mii = target.getInstrInfo();
+  const TargetInstrInfo& mii = target.getInstrInfo();
   
   
   MachineOpCode opCode = node->getOpCode();
@@ -732,7 +732,7 @@
                             RegToRefVecMap& regToRefVecMap,
                             ValueToDefVecMap& valueToDefVecMap)
 {
-  const MachineInstrInfo& mii = target.getInstrInfo();
+  const TargetInstrInfo& mii = target.getInstrInfo();
   
   // Build graph nodes for each VM instruction and gather def/use info.
   // Do both those together in a single pass over all machine instructions.