[llvm-commits] CVS: llvm/lib/CodeGen/LiveVariables.cpp MachineInstr.cpp PHIElimination.cpp PrologEpilogInserter.cpp RegAllocLocal.cpp RegAllocSimple.cpp
Chris Lattner
lattner at cs.uiuc.edu
Tue Jan 14 15:59:01 PST 2003
Changes in directory llvm/lib/CodeGen:
LiveVariables.cpp updated: 1.1 -> 1.2
MachineInstr.cpp updated: 1.68 -> 1.69
PHIElimination.cpp updated: 1.1 -> 1.2
PrologEpilogInserter.cpp updated: 1.4 -> 1.5
RegAllocLocal.cpp updated: 1.11 -> 1.12
RegAllocSimple.cpp updated: 1.37 -> 1.38
---
Log message:
Rename MachineInstrInfo -> TargetInstrInfo
---
Diffs of the changes:
Index: llvm/lib/CodeGen/LiveVariables.cpp
diff -u llvm/lib/CodeGen/LiveVariables.cpp:1.1 llvm/lib/CodeGen/LiveVariables.cpp:1.2
--- llvm/lib/CodeGen/LiveVariables.cpp:1.1 Mon Jan 13 14:01:16 2003
+++ llvm/lib/CodeGen/LiveVariables.cpp Tue Jan 14 15:58:41 2003
@@ -6,7 +6,7 @@
#include "llvm/CodeGen/LiveVariables.h"
#include "llvm/CodeGen/MachineInstr.h"
-#include "llvm/Target/MachineInstrInfo.h"
+#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Support/CFG.h"
#include "Support/DepthFirstIterator.h"
Index: llvm/lib/CodeGen/MachineInstr.cpp
diff -u llvm/lib/CodeGen/MachineInstr.cpp:1.68 llvm/lib/CodeGen/MachineInstr.cpp:1.69
--- llvm/lib/CodeGen/MachineInstr.cpp:1.68 Sun Jan 12 18:23:24 2003
+++ llvm/lib/CodeGen/MachineInstr.cpp Tue Jan 14 15:58:41 2003
@@ -6,19 +6,19 @@
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/Value.h"
#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/MachineInstrInfo.h"
+#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/MRegisterInfo.h"
using std::cerr;
// Global variable holding an array of descriptors for machine instructions.
// The actual object needs to be created separately for each target machine.
-// This variable is initialized and reset by class MachineInstrInfo.
+// This variable is initialized and reset by class TargetInstrInfo.
//
// FIXME: This should be a property of the target so that more than one target
// at a time can be active...
//
-extern const MachineInstrDescriptor *TargetInstrDescriptors;
+extern const TargetInstrDescriptor *TargetInstrDescriptors;
// Constructor for instructions with fixed #operands (nearly all)
MachineInstr::MachineInstr(MachineOpCode _opCode)
Index: llvm/lib/CodeGen/PHIElimination.cpp
diff -u llvm/lib/CodeGen/PHIElimination.cpp:1.1 llvm/lib/CodeGen/PHIElimination.cpp:1.2
--- llvm/lib/CodeGen/PHIElimination.cpp:1.1 Mon Jan 13 14:01:16 2003
+++ llvm/lib/CodeGen/PHIElimination.cpp Tue Jan 14 15:58:41 2003
@@ -10,7 +10,7 @@
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/SSARegMap.h"
#include "llvm/CodeGen/LiveVariables.h"
-#include "llvm/Target/MachineInstrInfo.h"
+#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
namespace {
Index: llvm/lib/CodeGen/PrologEpilogInserter.cpp
diff -u llvm/lib/CodeGen/PrologEpilogInserter.cpp:1.4 llvm/lib/CodeGen/PrologEpilogInserter.cpp:1.5
--- llvm/lib/CodeGen/PrologEpilogInserter.cpp:1.4 Sun Jan 12 18:23:41 2003
+++ llvm/lib/CodeGen/PrologEpilogInserter.cpp Tue Jan 14 15:58:41 2003
@@ -16,7 +16,7 @@
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/MRegisterInfo.h"
#include "llvm/Target/TargetFrameInfo.h"
-#include "llvm/Target/MachineInstrInfo.h"
+#include "llvm/Target/TargetInstrInfo.h"
namespace {
struct PEI : public MachineFunctionPass {
@@ -157,10 +157,10 @@
}
// Add code to restore the callee-save registers in each exiting block.
- const MachineInstrInfo &MII = Fn.getTarget().getInstrInfo();
+ const TargetInstrInfo &TII = Fn.getTarget().getInstrInfo();
for (MachineFunction::iterator FI = Fn.begin(), E = Fn.end(); FI != E; ++FI) {
// If last instruction is a return instruction, add an epilogue
- if (MII.isReturn(FI->back()->getOpcode())) {
+ if (TII.isReturn(FI->back()->getOpcode())) {
MBB = FI; I = MBB->end()-1;
for (unsigned i = 0, e = RegsToSave.size(); i != e; ++i) {
@@ -237,10 +237,10 @@
Fn.getTarget().getRegisterInfo()->emitPrologue(Fn);
// Add epilogue to restore the callee-save registers in each exiting block
- const MachineInstrInfo &MII = Fn.getTarget().getInstrInfo();
+ const TargetInstrInfo &TII = Fn.getTarget().getInstrInfo();
for (MachineFunction::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) {
// If last instruction is a return instruction, add an epilogue
- if (MII.isReturn(I->back()->getOpcode()))
+ if (TII.isReturn(I->back()->getOpcode()))
Fn.getTarget().getRegisterInfo()->emitEpilogue(Fn, *I);
}
}
Index: llvm/lib/CodeGen/RegAllocLocal.cpp
diff -u llvm/lib/CodeGen/RegAllocLocal.cpp:1.11 llvm/lib/CodeGen/RegAllocLocal.cpp:1.12
--- llvm/lib/CodeGen/RegAllocLocal.cpp:1.11 Sun Jan 12 18:25:40 2003
+++ llvm/lib/CodeGen/RegAllocLocal.cpp Tue Jan 14 15:58:41 2003
@@ -11,7 +11,7 @@
#include "llvm/CodeGen/SSARegMap.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/LiveVariables.h"
-#include "llvm/Target/MachineInstrInfo.h"
+#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "Support/Statistic.h"
#include "Support/CommandLine.h"
@@ -442,11 +442,11 @@
MachineBasicBlock::iterator I = MBB.begin();
for (; I != MBB.end(); ++I) {
MachineInstr *MI = *I;
- const MachineInstrDescriptor &MID = TM->getInstrInfo().get(MI->getOpcode());
+ const TargetInstrDescriptor &TID = TM->getInstrInfo().get(MI->getOpcode());
// Loop over the implicit uses, making sure that they are at the head of the
// use order list, so they don't get reallocated.
- if (const unsigned *ImplicitUses = MID.ImplicitUses)
+ if (const unsigned *ImplicitUses = TID.ImplicitUses)
for (unsigned i = 0; ImplicitUses[i]; ++i)
MarkPhysRegRecentlyUsed(ImplicitUses[i]);
@@ -498,7 +498,7 @@
}
// Loop over the implicit defs, spilling them as well.
- if (const unsigned *ImplicitDefs = MID.ImplicitDefs)
+ if (const unsigned *ImplicitDefs = TID.ImplicitDefs)
for (unsigned i = 0; ImplicitDefs[i]; ++i) {
unsigned Reg = ImplicitDefs[i];
spillPhysReg(MBB, I, Reg);
@@ -571,9 +571,9 @@
}
// Rewind the iterator to point to the first flow control instruction...
- const MachineInstrInfo &MII = TM->getInstrInfo();
+ const TargetInstrInfo &TII = TM->getInstrInfo();
I = MBB.end()-1;
- while (I != MBB.begin() && MII.isTerminatorInstr((*(I-1))->getOpcode()))
+ while (I != MBB.begin() && TII.isTerminatorInstr((*(I-1))->getOpcode()))
--I;
// Spill all physical registers holding virtual registers now.
Index: llvm/lib/CodeGen/RegAllocSimple.cpp
diff -u llvm/lib/CodeGen/RegAllocSimple.cpp:1.37 llvm/lib/CodeGen/RegAllocSimple.cpp:1.38
--- llvm/lib/CodeGen/RegAllocSimple.cpp:1.37 Sun Jan 12 18:26:08 2003
+++ llvm/lib/CodeGen/RegAllocSimple.cpp Tue Jan 14 15:58:41 2003
@@ -12,7 +12,7 @@
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/SSARegMap.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
-#include "llvm/Target/MachineInstrInfo.h"
+#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "Support/Statistic.h"
#include <iostream>
@@ -150,7 +150,7 @@
// a preliminary pass that will invalidate any registers that
// are used by the instruction (including implicit uses)
unsigned Opcode = MI->getOpcode();
- const MachineInstrDescriptor &Desc = TM->getInstrInfo().get(Opcode);
+ const TargetInstrDescriptor &Desc = TM->getInstrInfo().get(Opcode);
if (const unsigned *Regs = Desc.ImplicitUses)
while (*Regs)
RegsUsed[*Regs++] = true;
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