[llvm-commits] CVS: llvm/lib/Target/X86/Printer.cpp
Misha Brukman
brukman at cs.uiuc.edu
Wed Nov 20 12:57:01 PST 2002
Changes in directory llvm/lib/Target/X86:
Printer.cpp updated: 1.7 -> 1.8
---
Log message:
Check not only for MO_VirtualRegister, but MO_MachineRegister as well when
printing out assembly. After all, we want the real thing too.
---
Diffs of the changes:
Index: llvm/lib/Target/X86/Printer.cpp
diff -u llvm/lib/Target/X86/Printer.cpp:1.7 llvm/lib/Target/X86/Printer.cpp:1.8
--- llvm/lib/Target/X86/Printer.cpp:1.7 Mon Nov 18 00:56:51 2002
+++ llvm/lib/Target/X86/Printer.cpp Wed Nov 20 12:56:41 2002
@@ -71,6 +71,7 @@
const MRegisterInfo &RI) {
switch (MO.getType()) {
case MachineOperand::MO_VirtualRegister:
+ case MachineOperand::MO_MachineRegister:
if (MO.getReg() < MRegisterInfo::FirstVirtualRegister)
O << RI.get(MO.getReg()).Name;
else
@@ -137,14 +138,20 @@
// 2 Operands: this is for things like mov that do not read a second input
//
assert(((MI->getNumOperands() == 3 &&
- (MI->getOperand(0).getType()==MachineOperand::MO_VirtualRegister&&
- MI->getOperand(1).getType()==MachineOperand::MO_VirtualRegister))||
+ (MI->getOperand(0).getType()==MachineOperand::MO_VirtualRegister||
+ MI->getOperand(0).getType()==MachineOperand::MO_MachineRegister)
+ &&
+ (MI->getOperand(1).getType()==MachineOperand::MO_VirtualRegister||
+ MI->getOperand(1).getType()==MachineOperand::MO_MachineRegister))
+ ||
(MI->getNumOperands() == 2 &&
- (MI->getOperand(0).getType()==MachineOperand::MO_VirtualRegister)))
- && MI->getOperand(MI->getNumOperands()-1).getType() ==
- MachineOperand::MO_VirtualRegister &&
- "Bad format for MRMDestReg!");
-
+ (MI->getOperand(0).getType()==MachineOperand::MO_VirtualRegister||
+ MI->getOperand(0).getType()==MachineOperand::MO_MachineRegister)
+ && (MI->getOperand(MI->getNumOperands()-1).getType() ==
+ MachineOperand::MO_VirtualRegister||
+ MI->getOperand(MI->getNumOperands()-1).getType() ==
+ MachineOperand::MO_MachineRegister)))
+ && "Bad format for MRMDestReg!");
if (MI->getNumOperands() == 3 &&
MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
O << "**";
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