[llvm-commits] CVS: llvm/lib/Target/Sparc/EmitAssembly.cpp SparcInstrSelection.cpp SparcOptInfo.cpp SparcRegInfo.cpp

[Chris Lattner]

Changes in directory llvm/lib/Target/Sparc:

EmitAssembly.cpp updated: 1.66 -> 1.67
SparcInstrSelection.cpp updated: 1.77 -> 1.78
SparcOptInfo.cpp updated: 1.3 -> 1.4
SparcRegInfo.cpp updated: 1.76 -> 1.77

---
Log message:

Rename the redundant MachineOperand::getOperandType() to MachineOperand::getType()


---
Diffs of the changes:

Index: llvm/lib/Target/Sparc/EmitAssembly.cpp
diff -u llvm/lib/Target/Sparc/EmitAssembly.cpp:1.66 llvm/lib/Target/Sparc/EmitAssembly.cpp:1.67
--- llvm/lib/Target/Sparc/EmitAssembly.cpp:1.66	Sun Oct 27 20:01:37 2002
+++ llvm/lib/Target/Sparc/EmitAssembly.cpp	Sun Oct 27 22:45:29 2002
@@ -382,7 +382,7 @@
   else
     needBitsFlag = false;
   
-  switch (mop.getOperandType())
+  switch (mop.getType())
     {
     case MachineOperand::MO_VirtualRegister:
     case MachineOperand::MO_CCRegister:


Index: llvm/lib/Target/Sparc/SparcInstrSelection.cpp
diff -u llvm/lib/Target/Sparc/SparcInstrSelection.cpp:1.77 llvm/lib/Target/Sparc/SparcInstrSelection.cpp:1.78
--- llvm/lib/Target/Sparc/SparcInstrSelection.cpp:1.77	Sun Oct 27 18:28:31 2002
+++ llvm/lib/Target/Sparc/SparcInstrSelection.cpp	Sun Oct 27 22:45:29 2002
@@ -1106,7 +1106,7 @@
           for (unsigned i=0, numOps=minstr->getNumOperands(); i < numOps; ++i)
             {
               const MachineOperand& mop = minstr->getOperand(i);
-              if (mop.getOperandType() == MachineOperand::MO_VirtualRegister &&
+              if (mop.getType() == MachineOperand::MO_VirtualRegister &&
                   mop.getVRegValue() == unusedOp)
                 minstr->SetMachineOperandVal(i,
                                 MachineOperand::MO_VirtualRegister, fwdOp);


Index: llvm/lib/Target/Sparc/SparcOptInfo.cpp
diff -u llvm/lib/Target/Sparc/SparcOptInfo.cpp:1.3 llvm/lib/Target/Sparc/SparcOptInfo.cpp:1.4
--- llvm/lib/Target/Sparc/SparcOptInfo.cpp:1.3	Sat Oct 12 19:20:15 2002
+++ llvm/lib/Target/Sparc/SparcOptInfo.cpp	Sun Oct 27 22:45:29 2002
@@ -1,5 +1,7 @@
 //===-- SparcOptInfo.cpp --------------------------------------------------===//
 //
+// FIXME: Describe
+//
 //===----------------------------------------------------------------------===//
 
 #include "SparcInternals.h"
@@ -7,7 +9,6 @@
 #include "llvm/CodeGen/MachineInstr.h"
 #include <stdlib.h>
 
-
 //----------------------------------------------------------------------------
 // Function: IsUselessCopy
 // Decide whether a machine instruction is a redundant copy:
@@ -48,7 +49,7 @@
                    target.getRegInfo().getZeroRegNum()) ||
                   
                   /* or operand otherOp == 0 */
-                  (MI->getOperand(otherOp).getOperandType()
+                  (MI->getOperandType(otherOp)
                    == MachineOperand::MO_SignExtendedImmed &&
                    MI->getOperand(otherOp).getImmedValue() == 0));
         }


Index: llvm/lib/Target/Sparc/SparcRegInfo.cpp
diff -u llvm/lib/Target/Sparc/SparcRegInfo.cpp:1.76 llvm/lib/Target/Sparc/SparcRegInfo.cpp:1.77
--- llvm/lib/Target/Sparc/SparcRegInfo.cpp:1.76	Sun Oct 27 18:28:31 2002
+++ llvm/lib/Target/Sparc/SparcRegInfo.cpp	Sun Oct 27 22:45:29 2002
@@ -1599,11 +1599,10 @@
       // last operand is the def (unless for a store which has no def reg)
       MachineOperand& DefOp = DefInst->getOperand(DefInst->getNumOperands()-1);
       
-      if( DefOp.opIsDef() &&  
-	  DefOp.getOperandType() ==  MachineOperand::MO_MachineRegister) {
+      if (DefOp.opIsDef() &&
+          DefOp.getType() == MachineOperand::MO_MachineRegister) {
 	
 	// If the operand in DefInst is a def ...
-	
 	bool DefEqUse = false;
 	
 	std::vector<MachineInstr *>::iterator UseIt = DefIt;
@@ -1617,8 +1616,8 @@
 	  // for each inst (UseInst) that is below the DefInst do ...
 	  MachineOperand& UseOp = UseInst->getOperand(0);
 	  
-	  if( ! UseOp.opIsDef() &&  
-	      UseOp.getOperandType() == MachineOperand::MO_MachineRegister) {
+	  if (!UseOp.opIsDef() &&  
+	      UseOp.getType() == MachineOperand::MO_MachineRegister) {
 	    
 	    // if use is a register ...
 	    
@@ -1678,8 +1677,8 @@
 					PhyRegAlloc &PRA) const {
   MachineOperand& UseOp = UnordInst->getOperand(0);
 
-  if( ! UseOp.opIsDef() &&  
-      UseOp.getOperandType() ==  MachineOperand::MO_MachineRegister) {
+  if (!UseOp.opIsDef() &&
+      UseOp.getType() ==  MachineOperand::MO_MachineRegister) {
 
     // for the use of UnordInst, see whether there is a defining instr
     // before in the OrdVec
@@ -1695,7 +1694,7 @@
 	OrdInst->getOperand(OrdInst->getNumOperands()-1);
 
       if( DefOp.opIsDef() &&  
-	  DefOp.getOperandType() == MachineOperand::MO_MachineRegister) {
+	  DefOp.getType() == MachineOperand::MO_MachineRegister) {
 
 	//cerr << "\nDefining Ord Inst: " <<  *OrdInst;