[llvm-bugs] [Bug 235611] [AArch64][InstCombine] SVE shift/divide intrinsics simplified with IR shl/lshr/ashr/sdiv/udiv semantics (asr(x, x) -> 0, x/x -> 1)

LLVM Bugs via llvm-bugs llvm-bugs at lists.llvm.org
Sun Oct 25 23:26:53 PDT 2026

Previous message: [llvm-bugs] [Bug 235610] [AArch64][InstCombine] instCombineSVEDupqLane ignores the lane index of sve.dupq.lane
Next message: [llvm-bugs] [Bug 235612] [RISCV] Zvfbfmin vector sitofp/uitofp i32/i64 -> bf16 converts through f32 and rounds twice
Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

An HTML attachment was scrubbed...
URL: <http://lists.llvm.org/pipermail/llvm-bugs/attachments/20261026/a94db2b0/attachment.html>

Previous message: [llvm-bugs] [Bug 235610] [AArch64][InstCombine] instCombineSVEDupqLane ignores the lane index of sve.dupq.lane
Next message: [llvm-bugs] [Bug 235612] [RISCV] Zvfbfmin vector sitofp/uitofp i32/i64 -> bf16 converts through f32 and rounds twice
Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

More information about the llvm-bugs mailing list