[llvm-bugs] [Bug 154181] [X86][Sched][AlderlakeP] Align vector load/use gap to 5c and retune FP ports/latencies (FADD/FMA/FLOGIC/FSHUFFLE/FLOAD)

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Mon Aug 18 11:57:40 PDT 2025

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Previous message: [llvm-bugs] [Bug 154180] [X86][Sched][Atom] Correct InstRW mapping for CVTSI642SSrm to 8c/4uops group
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