[llvm-bugs] [Bug 78656] RISC-V x-register to vector-register via temp memory should be optimised to `vmv.vx` or `vmv.sx`

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Thu Jan 18 17:04:50 PST 2024

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Previous message: [llvm-bugs] [Bug 78651] [AArch64] Vector load of `i4` elements leads to scalar code
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