[llvm-bugs] [Bug 51878] New: Miscompile with aliased variable. DAGCombiner doesn't realize aliased variable alias?

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https://bugs.llvm.org/show_bug.cgi?id=51878

            Bug ID: 51878
           Summary: Miscompile with aliased variable. DAGCombiner doesn't
                    realize aliased variable alias?
           Product: libraries
           Version: trunk
          Hardware: PC
                OS: Linux
            Status: NEW
          Severity: enhancement
          Priority: P
         Component: Common Code Generator Code
          Assignee: unassignedbugs at nondot.org
          Reporter: mikael.holmen at ericsson.com
                CC: llvm-bugs at lists.llvm.org

Created attachment 25264
  --> https://bugs.llvm.org/attachment.cgi?id=25264&action=edit
bbi-60286.ll reproducer

llvm commit: 0dc461441eed

Reproduce with:
 llc -O1 -o - bbi-60286.ll

Result:
        movq    aliasVar at GOTPCREL(%rip), %rax
        movw    $5, (%rax)
        movq    cmVar at GOTPCREL(%rip), %rax
        movw    $7, (%rax)
        movw    $5, %ax
        retq

Since aliasVar is just an alias of cmVar I would have expected the return value
from the function to be 7, but it is 5.

During ISel we have

Initial selection DAG: %bb.0 'main:entry'
SelectionDAG has 14 nodes:
  t3: i64 = Constant<0>
      t0: ch = EntryToken
    t5: ch = store<(store (s16) into @aliasVar, align 1)> t0, Constant:i16<5>,
GlobalAddress:i64<i16* @aliasVar> 0, undef:i64
  t8: ch = store<(store (s16) into @cmVar, align 1)> t5, Constant:i16<7>,
GlobalAddress:i64<i16* @cmVar> 0, undef:i64
    t9: i16,ch = load<(load (s16) from @aliasVar, align 1)> t8,
GlobalAddress:i64<i16* @aliasVar> 0, undef:i64
  t12: ch,glue = CopyToReg t8, Register:i16 $ax, t9
  t13: ch = X86ISD::RET_FLAG t12, TargetConstant:i32<0>, Register:i16 $ax,
t12:1

which I think is ok, the two stores and then the load are chained together and
thus ordered, but then we get

Optimized lowered selection DAG: %bb.0 'main:entry'
SelectionDAG has 13 nodes:
  t0: ch = EntryToken
      t5: ch = store<(store (s16) into @aliasVar, align 1)> t0,
Constant:i16<5>, GlobalAddress:i64<i16* @aliasVar> 0, undef:i64
      t16: ch = store<(store (s16) into @cmVar, align 1)> t0, Constant:i16<7>,
GlobalAddress:i64<i16* @cmVar> 0, undef:i64
    t17: ch = TokenFactor t5, t16
  t12: ch,glue = CopyToReg t17, Register:i16 $ax, Constant:i16<5>
  t13: ch = X86ISD::RET_FLAG t12, TargetConstant:i32<0>, Register:i16 $ax,
t12:1

and now the stores are not ordered anymore, and the load has been removed and
the constant 5 is returned instead.

Is looks like the DAGCombiner doesn't realize aliasVar is actually the same
thing as cmVar.

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