[llvm-bugs] [Bug 50763] New: [MC][Thumb2] #-0 assembled as #INT_MIN instead
via llvm-bugs
llvm-bugs at lists.llvm.org
Thu Jun 17 20:57:22 PDT 2021
https://bugs.llvm.org/show_bug.cgi?id=50763
Bug ID: 50763
Summary: [MC][Thumb2] #-0 assembled as #INT_MIN instead
Product: libraries
Version: trunk
Hardware: PC
OS: Linux
Status: NEW
Severity: enhancement
Priority: P
Component: Backend: ARM
Assignee: unassignedbugs at nondot.org
Reporter: rprichard at google.com
CC: llvm-bugs at lists.llvm.org, smithp352 at googlemail.com,
Ties.Stuij at arm.com
The LLVM and GNU ARM assemblers recognize a special "negative zero" immediate
operand. The intent seems to have been to select an instruction encoding that
uses non-positive address offsets instead of non-negative offsets.
AFAICT they both use the same syntax: an immediate of value 0 whose first token
is a '-'. So #-(0) and #-(1-1) are treated specially, but #(-0) is not, because
its first token is '(' instead of '-'.
LLVM represents these offsets internally using INT_MIN. It uses the same
immediate parsing for non-address-offset immediates, and in that case, a #-0
operand is sometimes converted into an #INT_MIN operand. This seems wrong and
doesn't match the GNU assembler:
cat >test.s <<EOF
.syntax unified
.arch armv7-a
.text
.thumb
func:
mov r2, #-0
mov r2, #0x80000000
orn r2, r2, #-0
orn r2, r2, #0x80000000
add r2, #-0
add r2, #0x80000000
mvn r0, #-0
mvn r0, #0x80000000
EOF
llvm-mc --triple armv7a-linux test.s --filetype=obj -o test.o
llvm-objdump -d test.o
arm-linux-gnueabi-as test.s -c -o test.o
llvm-objdump -d test.o
LLVM output:
0: 4f f0 00 42 mov.w r2, #2147483648
4: 4f f0 00 42 mov.w r2, #2147483648
8: 62 f0 00 42 orn r2, r2, #2147483648
c: 62 f0 00 42 orn r2, r2, #2147483648
10: 02 f1 00 42 add.w r2, r2, #2147483648
14: 02 f1 00 42 add.w r2, r2, #2147483648
18: 6f f0 00 40 mvn r0, #2147483648
1c: 6f f0 00 40 mvn r0, #2147483648
GAS output:
0: 4f f0 00 02 mov.w r2, #0
4: 4f f0 00 42 mov.w r2, #2147483648
8: 62 f0 00 02 orn r2, r2, #0
c: 62 f0 00 42 orn r2, r2, #2147483648
10: 02 f1 00 02 add.w r2, r2, #0
14: 02 f1 00 42 add.w r2, r2, #2147483648
18: 6f f0 00 00 mvn r0, #0
1c: 6f f0 00 40 mvn r0, #2147483648
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