[llvm-bugs] [Bug 51322] New: [SchedModel] Missing ReadAdvance for the source (non dest) operand of RMW instructions.

[via llvm-bugs]

https://bugs.llvm.org/show_bug.cgi?id=51322

            Bug ID: 51322
           Summary: [SchedModel] Missing ReadAdvance for the source (non
                    dest) operand of RMW instructions.
           Product: libraries
           Version: trunk
          Hardware: PC
                OS: Windows NT
            Status: NEW
          Severity: enhancement
          Priority: P
         Component: Backend: X86
          Assignee: unassignedbugs at nondot.org
          Reporter: andrea.dibiagio at gmail.com
                CC: craig.topper at gmail.com, llvm-bugs at lists.llvm.org,
                    llvm-dev at redking.me.uk, pengfei.wang at intel.com,
                    spatel+llvm at rotateright.com

This is similar to bug 51318. However, it doesn't only affect ADC/SBB but any
RMW arithmetic opcode.

Example:
```
add  %eax, %eax
add  %eax, 4(%rsp)
```

> llvm-mca -mcpu=btver2 -iterations=1 -timeline

```
Timeline view:
Index     0123456789

[0,0]     DeER .   .   addl     %eax, %eax
[0,1]     D=eeeeeeER   addl     %eax, (%rsp)
```

EAX is written in 1cy. However, the load from RSP can start immediately, and
doesn't need to be delayed for 1cy.

This is the expected timeline:

```
Timeline view:
Index     012345678

[0,0]     DeER .  .   addl      %eax, %eax
[0,1]     DeeeeeeER   addl      %eax, 4(%rsp)
```

The issue is with the definition of WriteALURMW. it is caused by the absence of
a ReadAdvance for the register operand.


According to llvm-mc:

```
        addl    %eax, 4(%rsp)                   # <MCInst #380 ADD32mr
                                        #  <MCOperand Reg:58>
                                        #  <MCOperand Imm:1>
                                        #  <MCOperand Reg:0>
                                        #  <MCOperand Imm:4>
                                        #  <MCOperand Reg:0>
                                        #  <MCOperand Reg:22>>
```

The first 5 MCOperands are for the memory reference 4(%rsp).
The read at index #5 is currently not marked as ReadAfterLd.

Same problem affects ADC/SBB, for which we use an almost identical pattern,
except that WriteADCRMW is used instead of WriteALURMW.

For those instructions, we also need to mark with ReadAfterLd the implcit read
of EFLAGS.

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