[llvm-bugs] [Bug 50123] New: [X86] Failure to recognise generic shift from SSE PSLLQ intrinsic

[via llvm-bugs]

https://bugs.llvm.org/show_bug.cgi?id=50123

            Bug ID: 50123
           Summary: [X86] Failure to recognise generic shift from SSE
                    PSLLQ intrinsic
           Product: libraries
           Version: trunk
          Hardware: PC
                OS: Windows NT
            Status: NEW
          Severity: enhancement
          Priority: P
         Component: Scalar Optimizations
          Assignee: unassignedbugs at nondot.org
          Reporter: llvm-dev at redking.me.uk
                CC: david.bolvansky at gmail.com, lebedev.ri at gmail.com,
                    llvm-bugs at lists.llvm.org, nikita.ppv at gmail.com,
                    spatel+llvm at rotateright.com

We often fail to recognise that the _mm_sll_epi64 shift amount is in bounds,
allowing us to fold it to a generic shift. This happens for all SSE 'shift by
uniform variable' intrinsics.

https://simd.godbolt.org/z/vKT9YE5zM

#include <x86intrin.h>

__m128i shl_v2i64_mod31(__m128i val, __m128i amt) {
  amt = _mm_and_si128( amt, _mm_set1_epi32( 31 ) );
  return _mm_sll_epi64( val, _mm_unpacklo_epi32( amt, _mm_setzero_si128() ) );
}

__m128i shl_v2i64_mod31_alt(__m128i val, __m128i amt) {
  amt = _mm_and_si128( amt, _mm_setr_epi32( 31, 0, 0, 0 ) );
  return _mm_sll_epi64( val, amt );
}

define <2 x i64> @shl_v2i64_mod31(<2 x i64> %0, <2 x i64> %1){
  %3 = bitcast <2 x i64> %1 to <4 x i32>
  %4 = and <4 x i32> %3, <i32 31, i32 poison, i32 poison, i32 poison>
  %5 = insertelement <4 x i32> %4, i32 0, i32 1
  %6 = bitcast <4 x i32> %5 to <2 x i64>
  %7 = tail call <2 x i64> @llvm.x86.sse2.psll.q(<2 x i64> %0, <2 x i64> %6)
  ret <2 x i64> %7
}
declare <2 x i64> @llvm.x86.sse2.psll.q(<2 x i64>, <2 x i64>)

define <2 x i64> @shl_v2i64_mod31_alt(<2 x i64> %0, <2 x i64> %1) {
  %3 = and <2 x i64> %1, <i64 31, i64 poison>
  %4 = shufflevector <2 x i64> %3, <2 x i64> poison, <2 x i32> zeroinitializer
  %5 = shl <2 x i64> %0, %4
  ret <2 x i64> %5
}

I think we're just missing some bitcast/insertelement vector handling in
ValueTracking.

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