[llvm-bugs] [Bug 50035] New: x86/GlobalISel broken because TableGen does not understand special case getSubClassWithSubReg

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https://bugs.llvm.org/show_bug.cgi?id=50035

            Bug ID: 50035
           Summary: x86/GlobalISel broken because TableGen does not
                    understand special case getSubClassWithSubReg
           Product: libraries
           Version: trunk
          Hardware: PC
                OS: Linux
            Status: NEW
          Severity: enhancement
          Priority: P
         Component: Backend: X86
          Assignee: unassignedbugs at nondot.org
          Reporter: Matthew.Arsenault at amd.com
                CC: craig.topper at gmail.com, llvm-bugs at lists.llvm.org,
                    llvm-dev at redking.me.uk, pengfei.wang at intel.com,
                    spatel+llvm at rotateright.com

This testcase fails the verifier because tablegen does not expect the target to
modify the behavior of getSubClassWithSubReg:

; RUN: llc -global-isel -mtriple=i386-linux-gnu -verify-machineinstrs < %s

target triple = "i386-linux-gnu"

define i32 @foo(i32* %ptr) {
  %load = load volatile i32, i32* %ptr
  %mask = and i32 %load, 255
  ret i32 %mask
}



This is selected by this pattern:

// r & (2^8-1) ==> movz
def : Pat<(and GR32:$src1, 0xff),
          (MOVZX32rr8 (EXTRACT_SUBREG GR32:$src1, sub_8bit))>;

and subsequently fails the verifier:

bb.1 (%ir-block.0):
  %0:gr32 = MOV32rm %fixed-stack.0, 1, $noreg, 0, $noreg :: (invariant load 4
from %fixed-stack.0, align 16)
  %2:gr32 = MOV32rm %0:gr32, 1, $noreg, 0, $noreg :: (volatile load 4 from
%ir.ptr)
  %5:gr8 = COPY %2.sub_8bit:gr32
  %4:gr32 = MOVZX32rr8 %5:gr8
  $eax = COPY %4:gr32
  RET 0, implicit $eax

# End machine code for function foo.

*** Bad machine code: Invalid register class for subregister index ***
- function:    foo
- basic block: %bb.1  (0x9d02698)
- instruction: %5:gr8 = COPY %2.sub_8bit:gr32
- operand 1:   %2.sub_8bit:gr32


The equivalent of getSubClassWithSubReg called here ends up returning the
"wrong" answer, so the wrong register class for the subregister index is used:
https://github.com/llvm/llvm-project/blob/fbb9132e71a200c12f416d30f4528b58c6c283f2/llvm/utils/TableGen/GlobalISelEmitter.cpp#L4730

This is because x86 added a hacky case to bypass the ordinary register logic

const TargetRegisterClass *
X86RegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC,
                                       unsigned Idx) const {
  // The sub_8bit sub-register index is more constrained in 32-bit mode.
  // It behaves just like the sub_8bit_hi index.
  if (!Is64Bit && Idx == X86::sub_8bit)
    Idx = X86::sub_8bit_hi;

  // Forward to TableGen's default version.
  return X86GenRegisterInfo::getSubClassWithSubReg(RC, Idx);
}


I think the solution should be to avoid this special case, but I'm not sure
what that should look like. We currently don't have a way to indicate any
special treatment for register, register classes, or subregister index per
subtarget. Is there a way to restructure the x86 register definitions to avoid
this without one?

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