[llvm-bugs] [Bug 49982] New: opt -simplifycfg generates different code when dbg intrinsics are present

[via llvm-bugs]

https://bugs.llvm.org/show_bug.cgi?id=49982

            Bug ID: 49982
           Summary: opt -simplifycfg generates different code when dbg
                    intrinsics are present
           Product: libraries
           Version: trunk
          Hardware: PC
                OS: Linux
            Status: NEW
          Severity: enhancement
          Priority: P
         Component: Scalar Optimizations
          Assignee: unassignedbugs at nondot.org
          Reporter: mikael.holmen at ericsson.com
                CC: llvm-bugs at lists.llvm.org

Created attachment 24760
  --> https://bugs.llvm.org/attachment.cgi?id=24760&action=edit
scfg.ll reproducer

Reproduce with:
opt -simplifycfg -S -o - scfg.ll | opt -strip-debug -S -o res1.ll
and
opt -strip-debug -o - -S scfg.ll | opt -simplifycfg -S -o - | opt -strip-debug
-S -o res2.ll
diff res1.ll res2.ll

Result

11c11
< for.cond:                                         ; preds = %cond.end,
%lor.lhs.false, %land.lhs.true, %entry
---
> for.cond:                                         ; preds = %land.lhs.true21, %cond.end, %lor.lhs.false, %entry
14,19c14
<   br i1 %cmp, label %land.lhs.true, label %lor.lhs.false
< 
< land.lhs.true:                                    ; preds = %for.cond
<   %tobool.not = icmp ugt i32 %i5, 2
<   store i16 0, i16* getelementptr inbounds ([1 x i16], [1 x i16]* @f, i16 0,
i16 0), align 1
<   br label %for.cond
---
>   br i1 %cmp, label %land.lhs.true21, label %lor.lhs.false
25a21,24
>   store i16 0, i16* getelementptr inbounds ([1 x i16], [1 x i16]* @f, i16 0, i16 0), align 1
>   br label %for.cond
> 
> land.lhs.true21:                                  ; preds = %for.cond

This starts happening with 467b1f1cd2f277:
    [SimplifyCFG] Allow hoisting terminators only with HoistCommonInsts=false.

    As a side-effect of the change to default HoistCommonInsts to false
    early in the pipeline, we fail to convert conditional branch & phis to
    selects early on, which prevents vectorization for loops that contain
    conditional branches that effectively are selects (or if the loop gets
    vectorized, it will get vectorized very inefficiently).

    This patch updates SimplifyCFG to perform hoisting if the only
    instruction in both BBs is an equal branch. In this case, the only
    additional instructions are selects for phis, which should be cheap.

    Even though we perform hoisting, the benefits of this kind of hoisting
    should by far outweigh the negatives.

    For example, the loop in the code below will not get vectorized on
    AArch64 with the current default, but will with the patch. This is a
    fundamental pattern we should definitely vectorize. Besides that, I
    think the select variants should be easier to use for reasoning across
    other passes as well.

    https://clang.godbolt.org/z/sbjd8Wshx

    ```
    double clamp(double v) {
      if (v < 0.0)
        return 0.0;
      if (v > 6.0)
        return 6.0;
      return v;
    }

    void loop(double* X, double *Y) {
      for (unsigned i = 0; i < 20000; i++) {
        X[i] = clamp(Y[i]);
      }
    }
    ```

    Reviewed By: lebedev.ri

    Differential Revision: https://reviews.llvm.org/D100329

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