[llvm-bugs] [Bug 49819] New: [AMDGPU][MC][GFX9] Disassembler failed to decode SMEM with IMM=0 and OFFSET>127

[via llvm-bugs]

https://bugs.llvm.org/show_bug.cgi?id=49819

            Bug ID: 49819
           Summary: [AMDGPU][MC][GFX9] Disassembler failed to decode SMEM
                    with IMM=0 and OFFSET>127
           Product: libraries
           Version: trunk
          Hardware: PC
                OS: Windows NT
            Status: NEW
          Severity: enhancement
          Priority: P
         Component: Backend: AMDGPU
          Assignee: unassignedbugs at nondot.org
          Reporter: dpreobrazhensky at luxoft.com
                CC: llvm-bugs at lists.llvm.org

Debug build of disassembler triggers an assert when trying to decode the
following GFX9 code:

    0xc28948ff, 0x48b84d8b

The code is actually an illegal variant of s_atomic_add_x2:


SOFFSET      OFFSET                        OP     IMM GLC SOE SDATA   SBASE
|            |                             |        | |   |   |       |
0100100.0101.110000100110110001011  110000.10100010.0.1.0.1.0.0100011.111111  
|                                          |                  |       |
36                                         162                35      EXEC=126

The code is invalid for several reasons including:
  - unaligned SDATA
  - SBASE=EXEC
  - IMM=0 but OFFSET is not a valid SGPR

The last issue caused disassembler to assert.

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