[llvm-bugs] [Bug 47518] New: [AMDGPU][MC] Incorrect error position

[via llvm-bugs]

https://bugs.llvm.org/show_bug.cgi?id=47518

            Bug ID: 47518
           Summary: [AMDGPU][MC] Incorrect error position
           Product: libraries
           Version: trunk
          Hardware: PC
                OS: All
            Status: NEW
          Severity: enhancement
          Priority: P
         Component: Backend: AMDGPU
          Assignee: unassignedbugs at nondot.org
          Reporter: dpreobrazhensky at luxoft.com
                CC: llvm-bugs at lists.llvm.org

In many cases assembler does show error position or indicates a position
incorrectly.

Examples:

    // Incorrect error position, should point at '0x1FFFFF'
    gfx9> s_atc_probe 0, s[4:5], 0x1FFFFF
    _test.s:1:13: error: expected a 21-bit signed offset
    s_atc_probe 0, s[4:5], 0x1FFFFF
                ^

    // Error position is correct for gfx8 but incorrect for gfx9
    gfx8> global_load_dword v1, v[3:4], off dlc
    _test.s:3:35: error: invalid operand for instruction
    global_load_dword v1, v[3:4], off dlc
                                      ^
    gfx8> global_load_dword v1, v[3:4], off dlc
    _test.s:3:38: error: failed parsing operand.
    global_load_dword v1, v[3:4], off dlc
                                         ^

    // Incorrect error position, should point at '3'
    gfx8> ds_swizzle_b32 v8, v2 offset:swizzle(REVERSE,3)
    _test.s:1:45: error: group size must be a power of two
    ds_swizzle_b32 v8, v2 offset:swizzle(REVERSE,3)
                                                ^

    // Incorrect error position, should point at '33'
    gfx8> s_setreg_b32  hwreg(3,33,33), s2
    _test.s:1:15: error: invalid bit offset: only 5-bit values are legal
    s_setreg_b32  hwreg(3,33,33), s2
                  ^

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