[llvm-bugs] [Bug 47406] New: [X86][SSE] Incorrect domain register move to XMM0 for BLENDV instructons
via llvm-bugs
llvm-bugs at lists.llvm.org
Thu Sep 3 05:03:04 PDT 2020
https://bugs.llvm.org/show_bug.cgi?id=47406
Bug ID: 47406
Summary: [X86][SSE] Incorrect domain register move to XMM0 for
BLENDV instructons
Product: libraries
Version: trunk
Hardware: PC
OS: Windows NT
Status: NEW
Severity: enhancement
Priority: P
Component: Backend: X86
Assignee: unassignedbugs at nondot.org
Reporter: llvm-dev at redking.me.uk
CC: craig.topper at gmail.com, llvm-bugs at lists.llvm.org,
llvm-dev at redking.me.uk, spatel+llvm at rotateright.com
The SSE variants of PBLENDVB/BLENDVPD must move the condition mask to XMM0, but
the move instruction that is used is always MOVAPS, not MOVDQA/MOVAPD.
https://simd.godbolt.org/z/Tdx169
define <16 x i8> @blend_slt_v16i8(<16 x i8> %0, <16 x i8> %1, <16 x i8> %2) {
%4 = icmp slt <16 x i8> %2, zeroinitializer
%5 = select <16 x i1> %4, <16 x i8> %1, <16 x i8> %0
ret <16 x i8> %5
}
define <4 x float> @blend_slt_v4f32(<4 x float> %0, <4 x float> %1, <4 x i32>
%2) {
%4 = icmp slt <4 x i32> %2, zeroinitializer
%5 = select <4 x i1> %4, <4 x float> %1, <4 x float> %0
ret <4 x float> %5
}
define <2 x double> @blend_slt_v2f64(<2 x double> %0, <2 x double> %1, <2 x
i64> %2) {
%4 = icmp slt <2 x i64> %2, zeroinitializer
%5 = select <2 x i1> %4, <2 x double> %1, <2 x double> %0
ret <2 x double> %5
}
llc -mattr=+sse4.1
blend_slt_v16i8: # @blend_slt_v16i8
movdqa %xmm0, %xmm3
movaps %xmm2, %xmm0
pblendvb %xmm0, %xmm1, %xmm3
movdqa %xmm3, %xmm0
retq
blend_slt_v4f32: # @blend_slt_v4f32
movaps %xmm0, %xmm3
movaps %xmm2, %xmm0
blendvps %xmm0, %xmm1, %xmm3
movaps %xmm3, %xmm0
retq
blend_slt_v2f64: # @blend_slt_v2f64
movapd %xmm0, %xmm3
movaps %xmm2, %xmm0
blendvpd %xmm0, %xmm1, %xmm3
movapd %xmm3, %xmm0
retq
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