[llvm-bugs] [Bug 45975] New: [X86] Split masked integer vector stores into vXi32/vXi64 variants

[via llvm-bugs]

https://bugs.llvm.org/show_bug.cgi?id=45975

            Bug ID: 45975
           Summary: [X86] Split masked integer vector stores into
                    vXi32/vXi64 variants
           Product: libraries
           Version: trunk
          Hardware: PC
                OS: Windows NT
            Status: NEW
          Severity: enhancement
          Priority: P
         Component: Backend: X86
          Assignee: unassignedbugs at nondot.org
          Reporter: llvm-dev at redking.me.uk
                CC: craig.topper at gmail.com, llvm-bugs at lists.llvm.org,
                    llvm-dev at redking.me.uk, spatel+llvm at rotateright.com

All x86 CPUs have very different costs/behaviours for vXi32 and vXi64 masked
stores, we need to split these classes so we can use them without so many
overrides.

def  WriteVecMaskedStore  : SchedWrite;
def  WriteVecMaskedStoreY : SchedWrite;

should be:

def  WriteVecMaskedStore32  : SchedWrite;
def  WriteVecMaskedStore64  : SchedWrite;
def  WriteVecMaskedStore32Y : SchedWrite;
def  WriteVecMaskedStoreY64 : SchedWrite;

Similar to what we have for masked float vector stores:

def  WriteFMaskedStore32  : SchedWrite;
def  WriteFMaskedStore64  : SchedWrite;
def  WriteFMaskedStore32Y : SchedWrite;
def  WriteFMaskedStore64Y : SchedWrite;

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