[llvm-bugs] [Bug 46401] New: [AMDGPU][MC] Some of invalid opcodes can be disassembled but break code emitter

[via llvm-bugs]

https://bugs.llvm.org/show_bug.cgi?id=46401

            Bug ID: 46401
           Summary: [AMDGPU][MC] Some of invalid opcodes can be
                    disassembled but break code emitter
           Product: libraries
           Version: trunk
          Hardware: PC
                OS: All
            Status: NEW
          Severity: enhancement
          Priority: P
         Component: Backend: AMDGPU
          Assignee: unassignedbugs at nondot.org
          Reporter: dpreobrazhensky at luxoft.com
                CC: llvm-bugs at lists.llvm.org

Some limitations have recently been added on use of f16 inline constants
(change 5f5f566). As a result many previously valid encodings become invalid.
Disassembler is still able to decode them but some of these break code emitter.
For example, the following GFX9 code:

    0xf9,0x72,0x0a,0x7e,0xf0,0x06,0x86,0x00

may be correctly disassembled to an instruction shown below:

    v_cvt_f16_u16_sdwa v5, 0x3800 dst_sel:DWORD dst_unused:UNUSED_PAD
src0_sel:DWORD

However adding '-show-encoding' option breaks code emitter (debug build only).

I updated and run all script-generated tests and found out that the issue
manifests itself with GFX9 SDWA only. However looks like the problem is more
generic. In many cases code emitter manages to encode invalid instructions w/o
breakage.

We should probably revise errors handling in emitter - either relax some checks
or add a mode with these checks disabled. Or we could validate MCInst after
disassembly but before dumping encoding.

-- 
You are receiving this mail because:
You are on the CC list for the bug.
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.llvm.org/pipermail/llvm-bugs/attachments/20200619/0c114795/attachment.html>