[llvm-bugs] [Bug 46247] New: [Simple Register Coalescing] Assertion `VNI && "No live value at use."' failed.

[via llvm-bugs]

https://bugs.llvm.org/show_bug.cgi?id=46247

            Bug ID: 46247
           Summary: [Simple Register Coalescing]  Assertion `VNI && "No
                    live value at use."' failed.
           Product: libraries
           Version: trunk
          Hardware: PC
                OS: Linux
            Status: NEW
          Severity: normal
          Priority: P
         Component: Register Allocator
          Assignee: unassignedbugs at nondot.org
          Reporter: paulsson at linux.vnet.ibm.com
                CC: llvm-bugs at lists.llvm.org, quentin.colombet at gmail.com

Created attachment 23592
  --> https://bugs.llvm.org/attachment.cgi?id=23592&action=edit
reduced testcase

I found a test case which which triggered this assert with machine DCE
disabled. In the reduced test case, it seems that the whole block is in fact
dead and it would normally become an empty block after Machine DCE. However, if
run with 

llc -mtriple=s390x-linux-gnu -mcpu=z15 -O3 -o out.s tc_nolivevalatuse.ll
-disable-machine-dce -misched=shuffle

, the RegisterCoalescer deletes a lot of dead defs, but not all of them. Three
instructions remain, and the mischeduler will then be run and trigger the
assert.

It seems that the RegisterCoalescer is not updating data structures correctly
while deleting instructions.

llvm-project/llvm/lib/CodeGen/MachineScheduler.cpp:1144: void
llvm::ScheduleDAGMILive::updatePressureDiffs(llvm::ArrayRef<llvm::RegisterMaskPair>):
Assertion `VNI && "No live value at use."' failed.
...
#8 0x000002aa24927b36 llvm::ScheduleDAGMILive::updatePressureDiffs
...

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