[llvm-bugs] [Bug 46912] New: Request merge of various AArch64 SVE fixes onto the LLVM 11 Release branch

[via llvm-bugs]

https://bugs.llvm.org/show_bug.cgi?id=46912

            Bug ID: 46912
           Summary: Request merge of various AArch64 SVE fixes onto the
                    LLVM 11 Release branch
           Product: libraries
           Version: 11.0
          Hardware: All
                OS: All
            Status: NEW
          Severity: normal
          Priority: P
         Component: Backend: AArch64
          Assignee: unassignedbugs at nondot.org
          Reporter: sander.desmalen at arm.com
                CC: arnaud.degrandmaison at arm.com,
                    llvm-bugs at lists.llvm.org, smithp352 at googlemail.com,
                    Ties.Stuij at arm.com

Hello, would it be possible to have the following patches cherry-picked onto
the LLVM 11 release branch?

These are various fixes related to CodeGen for AArch64 SVE and/or scalable
vectors (for which SVE is the only target that supports it atm). Practically
all of the fixes are isolated to SVE and scalable vectors, so behavioural
changes are only exhibited when compiling for +sve. Any changes that are *not*
in lib/Target/AArch64 are of the kind: if(VT.isScalableVector) { /* bail out,
or do something else */ }

Fixes for various SVE bugs:
- 23ad660b5d34930b2b5362f1bba63daee78f6aa4 [SVE][CodeGen] At -O0 fallback to
DAG ISel when translating alloca with scalable types
- 9ad7c980bb47edd7db8f8db828b487cc7dfc9921 [SVE] Don't consider scalable vector
types in SLPVectorizerPass::vectorizeChainsInBlock
- 207877175944656bd9b52d36f391a092854572be [SVE][CodeGen] Add simple integer
add tests for SVE tuple types
- f43b5c7a76ab83dcc80e6769d41d5c4b761312b1 [SVE] Add checks for no warnings in
CodeGen/AArch64/sve-sext-zext.ll
- 5d84eafc6b86a42e261af8d753c3a823e0e7c67e [CodeGen] Remove calls to
getVectorNumElements in DAGTypeLegalizer::SplitVecOp_EXTRACT_SUBVECTOR
- 14bc85e0ebb6c00c1672158ab6a692bfbb11e1cc [SVE] Don't use LocalStackAllocation
for SVE objects
- cda2eb3ad2bbe923e74d6eb083af196a0622d800 [AArch64][SVE] Fix epilogue for SVE
when the stack is realigned.
- 26b4ef3694973ea2fa656d3d3a7f67f16f135654 [AArch64][SVE] Don't align the last
SVE callee save.
- 54492a5843a34684ce21ae201dd8ca3e509288fd [AArch64][SVE] Don't support
fixedStack for SVE objects.
- 993c1a3219a8ae69f1d700183bf174d75f3815d4 [AArch64][SVE] Teach copyPhysReg to
copy ZPR2/3/4.
- bef56f7fe2382ed1476aa67a55626b364635b44e [AArch64][SVE] Correctly allocate
scavenging slot in presence of SVE.
- 9bacf1588583014538a0217add18f370acb95788 [AArch64][SVE] Fix PCS for functions
taking/returning scalable types.
- b8f765a1e17f8d212ab1cd8f630d35adc7495556 [AArch64][SVE] Add support for trunc
to <vscale x N x i1>.


To apply (the first patch has merely a superficial conflict):

  $ git cherry-pick --strategy=recursive -X theirs
b8f765a1e17f8d212ab1cd8f630d35adc7495556
  $ git cherry-pick 9bacf1588583014538a0217add18f370acb95788
bef56f7fe2382ed1476aa67a55626b364635b44e
993c1a3219a8ae69f1d700183bf174d75f3815d4
54492a5843a34684ce21ae201dd8ca3e509288fd
26b4ef3694973ea2fa656d3d3a7f67f16f135654
cda2eb3ad2bbe923e74d6eb083af196a0622d800
14bc85e0ebb6c00c1672158ab6a692bfbb11e1cc
5d84eafc6b86a42e261af8d753c3a823e0e7c67e
f43b5c7a76ab83dcc80e6769d41d5c4b761312b1
207877175944656bd9b52d36f391a092854572be
9ad7c980bb47edd7db8f8db828b487cc7dfc9921
23ad660b5d34930b2b5362f1bba63daee78f6aa4


The following patches are addressing mode improvements, so more optional, but
are a really like-to-have:
- adb28e0fb2b0e97ea9dce422c09b36979cf7cd2f [llvm][CodeGen] Addressing modes for
SVE ldN.
- dbeb184b7f54db2d3ef20ac153b1c77f81cf0b99 [NFC][AArch64] Replace some template
methods/invocations...
- 809600d6642773f71245f76995dab355effc73af [llvm][sve] Reg + Imm addressing
mode for ld1ro.

To apply:
  $ git cherry-pick 809600d6642773f71245f76995dab355effc73af
dbeb184b7f54db2d3ef20ac153b1c77f81cf0b99
adb28e0fb2b0e97ea9dce422c09b36979cf7cd2f


Please let me know if you have any questions and/or concerns!

Thanks,

Sander

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