[llvm-bugs] [Bug 44526] New: ComputeKnownBits - minimum guaranteed leading/trailing zeros in logical right/left shifts

[via llvm-bugs]

https://bugs.llvm.org/show_bug.cgi?id=44526

            Bug ID: 44526
           Summary: ComputeKnownBits - minimum guaranteed leading/trailing
                    zeros in logical right/left shifts
           Product: libraries
           Version: trunk
          Hardware: PC
                OS: Windows NT
            Status: NEW
          Severity: enhancement
          Priority: P
         Component: Common Code Generator Code
          Assignee: unassignedbugs at nondot.org
          Reporter: llvm-dev at redking.me.uk
                CC: lebedev.ri at gmail.com, llvm-bugs at lists.llvm.org,
                    nikita.ppv at gmail.com, nunoplopes at sapo.pt,
                    regehr at cs.utah.edu, spatel+llvm at rotateright.com

As detailed in: https://blog.regehr.org/archives/1709

define i32 @foo(i32) {
  %a = lshr i32 4, %0
  ret i32 %a
}

None of our ComputeKnownBits implementations make use of the fact that logical
left/right shifts will at least retain the trailing/leading zeros of the
shifted value.

I'm currently investigating the SelectionDAG implementation but the InstCombine
+ GlobalISel versions will need handling as well.

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