[llvm-bugs] [Bug 44521] New: [InstCombine] Select based on sign bit condition not canonicalized

[via llvm-bugs]

https://bugs.llvm.org/show_bug.cgi?id=44521

            Bug ID: 44521
           Summary: [InstCombine] Select based on sign bit condition not
                    canonicalized
           Product: libraries
           Version: trunk
          Hardware: All
                OS: All
            Status: NEW
          Severity: enhancement
          Priority: P
         Component: Scalar Optimizations
          Assignee: unassignedbugs at nondot.org
          Reporter: nikita.ppv at gmail.com
                CC: llvm-bugs at lists.llvm.org

The following stay invariant under -instcombine:

define i8 @sign_select_scalar_sgt(i8 %cond, i8 %tval, i8 %fval) {
  %cmp = icmp sgt i8 %cond, -1
  %res = select i1 %cmp, i8 %fval, i8 %tval
  ret i8 %res
}
define i8 @sign_select_scalar_slt(i8 %cond, i8 %tval, i8 %fval) {
  %cmp = icmp slt i8 %cond, 0
  %res = select i1 %cmp, i8 %tval, i8 %fval
  ret i8 %res
}
define <4 x i8> @sign_select_vec_sgt(<4 x i8> %cond, <4 x i8> %tval, <4 x i8>
%fval) {
  %cmp = icmp sgt <4 x i8> %cond, <i8 -1, i8 -1, i8 -1, i8 -1>
  %res = select <4 x i1> %cmp, <4 x i8> %fval, <4 x i8> %tval
  ret <4 x i8> %res
}
define <4 x i8> @sign_select_vec_slt(<4 x i8> %cond, <4 x i8> %tval, <4 x i8>
%fval) {
  %cmp = icmp slt <4 x i8> %cond, zeroinitializer
  %res = select <4 x i1> %cmp, <4 x i8> %tval, <4 x i8> %fval
  ret <4 x i8> %res
}

I would expect that this gets canonicalized one way or another (<0 probably).

Noticed this when some InstCombine worklist order changes resulted in the above
patterns getting flipped in places.

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