[llvm-bugs] [Bug 47132] New: vector ZERO_EXTEND gets scalarized

[via llvm-bugs]

https://bugs.llvm.org/show_bug.cgi?id=47132

            Bug ID: 47132
           Summary: vector ZERO_EXTEND gets scalarized
           Product: libraries
           Version: trunk
          Hardware: PC
                OS: Linux
            Status: NEW
          Severity: enhancement
          Priority: P
         Component: Backend: SystemZ
          Assignee: unassignedbugs at nondot.org
          Reporter: paulsson at linux.vnet.ibm.com
                CC: llvm-bugs at lists.llvm.org

Created attachment 23844
  --> https://bugs.llvm.org/attachment.cgi?id=23844&action=edit
test case

The (first) DAGCombiner will replace a DAG like:

       t8: v2f64 = BUILD_VECTOR ConstantFP:f64<0.000000e+00>,
ConstantFP:f64<0.000000e+00>
     t10: v2i1 = setcc t2, t8, setoeq:ch
   t11: v2i32 = zero_extend t10

in visitZERO_EXTEND() to

          t8: v2f64 = BUILD_VECTOR ConstantFP:f64<0.000000e+00>,
ConstantFP:f64<0.000000e+00>
        t16: v2i64 = setcc t2, t8, setoeq:ch
      t17: v2i32 = truncate t16
     t19: v2i32 = BUILD_VECTOR Constant:i32<1>, Constant:i32<1>
   t20: v2i32 = and t17, t19

This works only with a SETCC operand (DAGCombiner.cpp:10482), so an OR of two
SETCC results is currently unhandled, and the type legalizer will then
scalarize the zero_extend:

t11: v2i32 = zero_extend t10
 WidenVectorResult()
   WidenVecRes_Convert() -> scalarization

Zero extending a vector of i1 is not quite simple, as it involves first
truncating / extending the vector select result, and then and:ing each element
with 1. Perhaps it would a custom DAG combine (pre-legalize types) is the right
approach given this? Or coudl the common-code that currently just handles a
SETCC operand be extended to handle this type of case, maybe?

The DAGTypeLegalizer wants to either widen the InVT (v2i1) or have the
InWidenVT to be legal (v4i1), or it will scalarize. I am not sure if that could
be made to work, but at first glance it doesn't look right.


llc -O3 -mcpu=z14 -o - ./tc_or_i1.ll -debug-only="isel,legalize-types"

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