[llvm-bugs] [Bug 43542] New: Poor codegen for targets with no native shifts

[via llvm-bugs]

https://bugs.llvm.org/show_bug.cgi?id=43542

            Bug ID: 43542
           Summary: Poor codegen for targets with no native shifts
           Product: libraries
           Version: trunk
          Hardware: All
                OS: All
            Status: NEW
          Severity: normal
          Priority: P
         Component: Common Code Generator Code
          Assignee: unassignedbugs at nondot.org
          Reporter: joan.lluch at icloud.com
                CC: llvm-bugs at lists.llvm.org

This is a recurrent problem that I have found while developing backends for
simple 8 bit or 16 bit targets. The problem is rather generic and related with
the fact that LLVM considers shifts as cheap operations, without giving the
targets the opportunity to tell the contrary. This causes poor codegen for
targets with expensive shifts, such as the majority of 8 bit and 16 bit
processors, including trunk targets (MSP430, AVR), and new targets in
development.

I am showing just one instance of this happening for the MSP430 target.
However, I strongly suggest that this problem is considered as a LLVM wide bug
and as such a generic solution is proposed. In this case the offender is found
in DAGCombiner::SimplifySelectCC

Consider the following C code:

int select_and( int a,  int b)
{
  unsigned int r = 0;
  if (a & 2)
    r = b;

  return r;
}

This is compiled into :

; Function Attrs: norecurse nounwind readnone
define dso_local i16 @select_and(i16 %a, i16 %b) local_unnamed_addr #0 {
entry:
  %and = and i16 %a, 2
  %tobool = icmp eq i16 %and, 0
  %spec.select = select i1 %tobool, i16 0, i16 %b
  ret i16 %spec.select
}

Which is then turned into this for the MSP430 target

        .text
        .file   "main.c"
        .globl  select_and
        .p2align        1
        .type   select_and, at function
select_and:
        mov.b   r12, r12
        swpb    r12
        add     r12, r12
        add     r12, r12
        add     r12, r12
        add     r12, r12
        add     r12, r12
        add     r12, r12
        swpb    r12
        sxt     r12
        rra     r12
        rra     r12
        rra     r12
        rra     r12
        rra     r12
        rra     r12
        rra     r12
        and     r13, r12
        ret
.Lfunc_end0:
        .size   select_and, .Lfunc_end0-select_and

This is suboptimal and ultimatelly caused by the following fold:

(select_cc seteq (and x, y), 0, 0, A) -> (and (shr (shl x)) A)

that happens in DAGCombiner::SimplifySelectCC

As said this is only ONE case where selects or other instructions are replaced
by expensive shifts, ultimately creating long and slow code on targets with no
native support of multiple shifts.

John

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