[llvm-bugs] [Bug 44025] New: Ashr does not alter sign bit - could look past ashr, backend fails to undo transform

[via llvm-bugs]

https://bugs.llvm.org/show_bug.cgi?id=44025

            Bug ID: 44025
           Summary: Ashr does not alter sign bit - could look past ashr,
                    backend fails to undo transform
           Product: libraries
           Version: trunk
          Hardware: PC
                OS: Linux
            Status: NEW
          Severity: enhancement
          Priority: P
         Component: Backend: X86
          Assignee: unassignedbugs at nondot.org
          Reporter: lebedev.ri at gmail.com
                CC: craig.topper at gmail.com, llvm-bugs at lists.llvm.org,
                    llvm-dev at redking.me.uk, spatel+llvm at rotateright.com

I'm not sure how relevant this is, but i noticed this while looking at some
code.
We could have something like:

#include <algorithm>
struct S {
    int a, b;
};
unsigned long zz(S s) {
    return std::abs(static_cast<signed long>(s.a)); // or s.b
}

Currently it ends as 

define dso_local i64 @_Z2zz1S(i64 %0) local_unnamed_addr #0 {
  %2 = shl i64 %0, 32
  %3 = ashr exact i64 %2, 32
  %4 = sub nsw i64 0, %3
  %5 = icmp slt i64 %3, 0
  %6 = select i1 %5, i64 %4, i64 %3
  ret i64 %6
}

        movsxd  rcx, edi
        mov     rax, rcx
        neg     rax
        cmovl   rax, rcx

But we are checking sign bit of %3, which is ashr, and it preserves sign bit.
We could look past it: https://rise4fun.com/Alive/iANsl

But that exposes a weakness in backend part - it doesn't know that it could
undo such transform, and not perform the test:

        movsxd  rcx, edi
        shl     rdi, 32
        mov     rax, rcx
        neg     rax
        test    rdi, rdi
        cmovns  rax, rcx

https://godbolt.org/z/Hr4ceT

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