[llvm-bugs] [Bug 41280] New: [AMDGPU][MC] Incorrect parsing of registers

[via llvm-bugs]

https://bugs.llvm.org/show_bug.cgi?id=41280

            Bug ID: 41280
           Summary: [AMDGPU][MC] Incorrect parsing of registers
           Product: libraries
           Version: trunk
          Hardware: PC
                OS: All
            Status: NEW
          Severity: enhancement
          Priority: P
         Component: Backend: AMDGPU
          Assignee: unassignedbugs at nondot.org
          Reporter: dpreobrazhensky at luxoft.com
                CC: llvm-bugs at lists.llvm.org

In many cases assembler does not report an error when an invalid register
syntax is detected, instead it resorts to parse an immediate. However some
tokens have already been consumed in an attempt to parse a register which
result in weird behavior.

Examples:

// Each of the following lines is assembled
// without errors and result in the same code as
// "s_mov_b32 s1, 1"

  s_mov_b32 s1, s 1
  s_mov_b32 s1, s[0 1
  s_mov_b32 s1, s[0:0 1
  s_mov_b32 s1, [s[0 1
  s_mov_b32 s1, [s[0:1] 1
  s_mov_b32 s1, [s0, 1
  s_mov_b32 s1, s999 1
  s_mov_b32 s1, s[1:2] 1
  s_mov_b32 s1, s[0:2] 1
  s_mov_b32 s1, xnack_mask_lo 1 // assuming xnack is not supported

// There is a similar issue with "off" handling.
// The following code is assembled without 
// errors and result in the same code as
// "exp mrt0 v1, v2, v3, off":

  exp mrt0 v1, v2, v3, v4000 off

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