[llvm-bugs] [Bug 42412] New: [InstCombine] and-mask + conditional "sext" -> and-mask + sext

[via llvm-bugs]

https://bugs.llvm.org/show_bug.cgi?id=42412

            Bug ID: 42412
           Summary: [InstCombine] and-mask + conditional "sext" ->
                    and-mask + sext
           Product: libraries
           Version: trunk
          Hardware: PC
                OS: Linux
            Status: NEW
          Severity: enhancement
          Priority: P
         Component: Scalar Optimizations
          Assignee: unassignedbugs at nondot.org
          Reporter: lebedev.ri at gmail.com
                CC: llvm-bugs at lists.llvm.org

There's also identical problem to https://bugs.llvm.org/show_bug.cgi?id=42389
with different bit buffer abstraction:
https://godbolt.org/z/po3_0Y
https://rise4fun.com/Alive/btQ

int bad(unsigned input, unsigned len) {
    unsigned diff = input & ((1 << len)-1);
    // If the first bit is 1 we need to turn this into a negative number
    if (diff >> (len - 1))
        diff -= (1 << len);
    return diff;
}
int good(unsigned input, unsigned len) {
    unsigned diff = input & ((1 << len)-1);
    diff <<= (32-len);
    diff = int(diff) >> (32-len);
    return diff;
}

Name: 
  %o3 = shl i32 1, %len
  %o4 = add nsw i32 %o3, -1
  %o5 = and i32 %o4, %data
  %o6 = add i32 %len, -1
  %o7 = lshr i32 %o5, %o6
  %o8 = icmp eq i32 %o7, 0
  %o9 = select i1 %o8, i32 0, i32 %o3
  %r = sub i32 %o5, %o9
=>
  %n3 = shl nsw i32 -1, %len
  %n4 = xor i32 %n3, -1
  %n5 = and i32 %n4, %data
  %n6 = sub i32 32, %len
  %n7 = shl i32 %n5, %n6
  %r = ashr i32 %n7, %n6

Did not analyse this one yet.

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