[llvm-bugs] [Bug 42397] New: SCEVExpander wrongly adds nsw to shl instruction

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https://bugs.llvm.org/show_bug.cgi?id=42397

            Bug ID: 42397
           Summary: SCEVExpander wrongly adds nsw to shl instruction
           Product: libraries
           Version: trunk
          Hardware: PC
                OS: Linux
            Status: NEW
          Severity: normal
          Priority: P
         Component: Global Analyses
          Assignee: unassignedbugs at nondot.org
          Reporter: pankaj.chawla at intel.com
                CC: llvm-bugs at lists.llvm.org

This SCEVExpander bug was exposed by a recent patch to add nuw/nsw flags when
generating code for SCEVMulExpr.

The test case IR looks like this-

%1 = load i16, i16* %arrayidx
%2 = and i16 %1, -32768

The SCEV form of %2 is this-
(-32768 * (%1 /u -32768))<nuw><nsw>

It has both nsw/nuw flags. The signed range of the second operand of
SCEVMulExpr (%1 /u -32768) is [0, 2). So it can be either 0 or 1.

But SCEVExpander uses shl to generate the multiply. The generated IR looks
something like this-

%7 = lshr i16 %gepload, 15
%8 = shl nuw nsw i16 %7, 15

%8 is later simplified to zero because according to langref it produces poison
otherwise -
If the nuw keyword is present, then the shift produces a poison value if it
shifts out any non-zero bits. If the nsw keyword is present, then the shift
produces a poison value if it shifts out any bits that disagree with the
resultant sign bit.

The shl instruction should not get nsw flag.

Here's instcombine checking for this edge condition when shifting by (bitwidth
- 1) -

https://github.com/llvm/llvm-project/blob/5e13cd2e61cb187f28d743c15141333530cc1adf/llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp#L177

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