[llvm-bugs] [Bug 42820] New: [RISCV][RV64] Lost zero extension while returning complex floating value

[via llvm-bugs]

https://bugs.llvm.org/show_bug.cgi?id=42820

            Bug ID: 42820
           Summary: [RISCV][RV64] Lost zero extension while returning
                    complex floating value
           Product: libraries
           Version: trunk
          Hardware: PC
                OS: Linux
            Status: NEW
          Severity: normal
          Priority: P
         Component: Backend: RISC-V
          Assignee: unassignedbugs at nondot.org
          Reporter: shiva0217 at gmail.com
                CC: llvm-bugs at lists.llvm.org

Created attachment 22313
  --> https://bugs.llvm.org/attachment.cgi?id=22313&action=edit
C source test case

Complex floating value for lp64 ABI will be returned by a single register.
So the imaginary part will be shift left 32-bits and or with the real part.
If the real part didn't do the zero extension to clear the upper bits, the
imaginary part may be corrupted by the or operation.

float _Complex
complex_add(float _Complex a, float _Complex b)
{
 return a + b;
}
RealResult = zero_extend(RealA + RealB)
ImageResult = ImageA + ImageB
Return (RealResult | (ImageResult << 32))

One way to fix the issue is to expand AssertZext to shifts if the value is
copied from x10 or x11. But it might be an overkilled method.

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