[llvm-bugs] [Bug 38861] New: Emit third operand for the rdhwr instruction on MIPS64 < R6

[via llvm-bugs]

https://bugs.llvm.org/show_bug.cgi?id=38861

            Bug ID: 38861
           Summary: Emit third operand for the rdhwr instruction on MIPS64
                    < R6
           Product: libraries
           Version: trunk
          Hardware: PC
                OS: All
            Status: NEW
          Severity: normal
          Priority: P
         Component: Backend: MIPS
          Assignee: unassignedbugs at nondot.org
          Reporter: simon at atanasyan.com
                CC: llvm-bugs at lists.llvm.org

MIPS ISAs before "Revision 6" do not support third operand for the rdhwr
instruction. But LLVM generates three-operands version of the instruction on
any MIPS64 ISAs. This is regression caused by r335162.

% cat test.ll
declare i8* @llvm.thread.pointer() nounwind readnone

define i8* @thread_pointer() {
  %1 = tail call i8* @llvm.thread.pointer()
  ret i8* %1
}

% llc -march=mips64 < test.ll
...
        rdhwr   $3, $29, 0

% llc -march=mips < test.ll
...
        rdhwr   $3, $29

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