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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW - Emit third operand for the rdhwr instruction on MIPS64 < R6"
href="https://bugs.llvm.org/show_bug.cgi?id=38861">38861</a>
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<th>Summary</th>
<td>Emit third operand for the rdhwr instruction on MIPS64 < R6
</td>
</tr>
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<th>Product</th>
<td>libraries
</td>
</tr>
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<th>Version</th>
<td>trunk
</td>
</tr>
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<th>Hardware</th>
<td>PC
</td>
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<th>OS</th>
<td>All
</td>
</tr>
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<th>Status</th>
<td>NEW
</td>
</tr>
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<th>Severity</th>
<td>normal
</td>
</tr>
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<th>Priority</th>
<td>P
</td>
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<th>Component</th>
<td>Backend: MIPS
</td>
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<th>Assignee</th>
<td>unassignedbugs@nondot.org
</td>
</tr>
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<th>Reporter</th>
<td>simon@atanasyan.com
</td>
</tr>
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<th>CC</th>
<td>llvm-bugs@lists.llvm.org
</td>
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<p>
<div>
<pre>MIPS ISAs before "Revision 6" do not support third operand for the rdhwr
instruction. But LLVM generates three-operands version of the instruction on
any MIPS64 ISAs. This is regression caused by r335162.
% cat test.ll
declare i8* @llvm.thread.pointer() nounwind readnone
define i8* @thread_pointer() {
%1 = tail call i8* @llvm.thread.pointer()
ret i8* %1
}
% llc -march=mips64 < test.ll
...
rdhwr $3, $29, 0
% llc -march=mips < test.ll
...
rdhwr $3, $29</pre>
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