[llvm-bugs] [Bug 39185] New: MIR parser doesn't have easy way to set !IsSSA

[via llvm-bugs]

https://bugs.llvm.org/show_bug.cgi?id=39185

            Bug ID: 39185
           Summary: MIR parser doesn't have easy way to set !IsSSA
           Product: libraries
           Version: trunk
          Hardware: PC
                OS: Linux
            Status: NEW
          Severity: enhancement
          Priority: P
         Component: GlobalISel
          Assignee: unassignedbugs at nondot.org
          Reporter: chisophugis at gmail.com
                CC: llvm-bugs at lists.llvm.org

Various MIR tests have a pattern like:

```
        %0 = COPY $r0
        %0 = COPY $r0  ; Force isSSA = false.
```



https://github.com/fuchsia-mirror/third_party-llvm/blob/70285a03596946657b49fed5ded6558050bb6e5b/test/CodeGen/AArch64/mlicm-stack-write-check.mir#L31


https://github.com/IITH-Compilers/LLVM-Loop-Profiler/blob/bdb32a89598f94808b8aae8819541eadadbcb3c2/test/CodeGen/Hexagon/expand-condsets-rm-reg.mir#L38


It would be nice if you could somehow just say `IsSSA: false` somewhere at the
top of the MIR test.

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