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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW - MIR parser doesn't have easy way to set !IsSSA"
href="https://bugs.llvm.org/show_bug.cgi?id=39185">39185</a>
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<th>Summary</th>
<td>MIR parser doesn't have easy way to set !IsSSA
</td>
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<tr>
<th>Product</th>
<td>libraries
</td>
</tr>
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<th>Version</th>
<td>trunk
</td>
</tr>
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<th>Hardware</th>
<td>PC
</td>
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<th>OS</th>
<td>Linux
</td>
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<th>Status</th>
<td>NEW
</td>
</tr>
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<th>Severity</th>
<td>enhancement
</td>
</tr>
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<th>Priority</th>
<td>P
</td>
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<th>Component</th>
<td>GlobalISel
</td>
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<th>Assignee</th>
<td>unassignedbugs@nondot.org
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</tr>
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<th>Reporter</th>
<td>chisophugis@gmail.com
</td>
</tr>
<tr>
<th>CC</th>
<td>llvm-bugs@lists.llvm.org
</td>
</tr></table>
<p>
<div>
<pre>Various MIR tests have a pattern like:
```
%0 = COPY $r0
%0 = COPY $r0 ; Force isSSA = false.
```
<a href="https://github.com/fuchsia-mirror/third_party-llvm/blob/70285a03596946657b49fed5ded6558050bb6e5b/test/CodeGen/AArch64/mlicm-stack-write-check.mir#L31">https://github.com/fuchsia-mirror/third_party-llvm/blob/70285a03596946657b49fed5ded6558050bb6e5b/test/CodeGen/AArch64/mlicm-stack-write-check.mir#L31</a>
<a href="https://github.com/IITH-Compilers/LLVM-Loop-Profiler/blob/bdb32a89598f94808b8aae8819541eadadbcb3c2/test/CodeGen/Hexagon/expand-condsets-rm-reg.mir#L38">https://github.com/IITH-Compilers/LLVM-Loop-Profiler/blob/bdb32a89598f94808b8aae8819541eadadbcb3c2/test/CodeGen/Hexagon/expand-condsets-rm-reg.mir#L38</a>
It would be nice if you could somehow just say `IsSSA: false` somewhere at the
top of the MIR test.</pre>
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</p>
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