[llvm-bugs] [Bug 39834] New: PowerPC wait encoding is invalid for e500mc

via llvm-bugs llvm-bugs at lists.llvm.org
Wed Nov 28 13:15:03 PST 2018


            Bug ID: 39834
           Summary: PowerPC wait encoding is invalid for e500mc
           Product: libraries
           Version: trunk
          Hardware: All
                OS: All
            Status: NEW
          Severity: enhancement
          Priority: P
         Component: Backend: PowerPC
          Assignee: unassignedbugs at nondot.org
          Reporter: vit9696 at avp.su
                CC: llvm-bugs at lists.llvm.org, nemanja.i.ibm at gmail.com

Power ISA 2.07B and 3.0B have different encodings for wait instruction
(0x7C00007C vs 0x7C00003C). We happen to partially support the latter, and
mistakingly emit the wrong opcode for targets like e500mc.

Power ISA 3.0B [1] on page 876 defines wait instruction in a way we have it In
def WAIT : XForm_24_sync<31, 30, (outs), (ins i32imm:$L),
                         "wait $L", IIC_LdStLoad, []>;

However, in Power ISA 2.07B [2] on page 791 the instruction with the same
mnemonic is encoded differently, for which the actual definition should be:
def WAIT : XForm_24_sync<31, 62, (outs), (ins i32imm:$L),
                         "wait $L", IIC_LdStLoad, []>;

The reference for e500mc [3] on page 6-371 also provides the waitrsv mnemonic,
and waitimpl mnemonic can be found in bintuils [4]. I believe the intention was
to support the 2.07B variant, which has neither of the two.

[1] https://ibm.box.com/s/1hzcwkwf8rbju5h9iyf44wm94amnlcrv
[2] https://ibm.box.com/s/jd5w15gz301s5b5dt375mshpq9c3lh4u
[3] https://www.nxp.com/files-static/32bit/doc/ref_manual/EREF_RM.pdf

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