<html>
    <head>
      <base href="https://bugs.llvm.org/">
    </head>
    <body><table border="1" cellspacing="0" cellpadding="8">
        <tr>
          <th>Bug ID</th>
          <td><a class="bz_bug_link 
          bz_status_NEW "
   title="NEW - PowerPC wait encoding is invalid for e500mc"
   href="https://bugs.llvm.org/show_bug.cgi?id=39834">39834</a>
          </td>
        </tr>

        <tr>
          <th>Summary</th>
          <td>PowerPC wait encoding is invalid for e500mc
          </td>
        </tr>

        <tr>
          <th>Product</th>
          <td>libraries
          </td>
        </tr>

        <tr>
          <th>Version</th>
          <td>trunk
          </td>
        </tr>

        <tr>
          <th>Hardware</th>
          <td>All
          </td>
        </tr>

        <tr>
          <th>OS</th>
          <td>All
          </td>
        </tr>

        <tr>
          <th>Status</th>
          <td>NEW
          </td>
        </tr>

        <tr>
          <th>Severity</th>
          <td>enhancement
          </td>
        </tr>

        <tr>
          <th>Priority</th>
          <td>P
          </td>
        </tr>

        <tr>
          <th>Component</th>
          <td>Backend: PowerPC
          </td>
        </tr>

        <tr>
          <th>Assignee</th>
          <td>unassignedbugs@nondot.org
          </td>
        </tr>

        <tr>
          <th>Reporter</th>
          <td>vit9696@avp.su
          </td>
        </tr>

        <tr>
          <th>CC</th>
          <td>llvm-bugs@lists.llvm.org, nemanja.i.ibm@gmail.com
          </td>
        </tr></table>
      <p>
        <div>
        <pre>Power ISA 2.07B and 3.0B have different encodings for wait instruction
(0x7C00007C vs 0x7C00003C). We happen to partially support the latter, and
mistakingly emit the wrong opcode for targets like e500mc.

Power ISA 3.0B [1] on page 876 defines wait instruction in a way we have it In
PPCInstrInfo.td:
def WAIT : XForm_24_sync<31, 30, (outs), (ins i32imm:$L),
                         "wait $L", IIC_LdStLoad, []>;

However, in Power ISA 2.07B [2] on page 791 the instruction with the same
mnemonic is encoded differently, for which the actual definition should be:
def WAIT : XForm_24_sync<31, 62, (outs), (ins i32imm:$L),
                         "wait $L", IIC_LdStLoad, []>;

The reference for e500mc [3] on page 6-371 also provides the waitrsv mnemonic,
and waitimpl mnemonic can be found in bintuils [4]. I believe the intention was
to support the 2.07B variant, which has neither of the two.

[1] <a href="https://ibm.box.com/s/1hzcwkwf8rbju5h9iyf44wm94amnlcrv">https://ibm.box.com/s/1hzcwkwf8rbju5h9iyf44wm94amnlcrv</a>
[2] <a href="https://ibm.box.com/s/jd5w15gz301s5b5dt375mshpq9c3lh4u">https://ibm.box.com/s/jd5w15gz301s5b5dt375mshpq9c3lh4u</a>
[3] <a href="https://www.nxp.com/files-static/32bit/doc/ref_manual/EREF_RM.pdf">https://www.nxp.com/files-static/32bit/doc/ref_manual/EREF_RM.pdf</a>
[4]
<a href="https://sourceware.org/git/?p=binutils-gdb.git;a=blob;f=opcodes/ppc-opc.c;h=bb311642d6a47824145122a16cabd6cff8272e58;hb=HEAD">https://sourceware.org/git/?p=binutils-gdb.git;a=blob;f=opcodes/ppc-opc.c;h=bb311642d6a47824145122a16cabd6cff8272e58;hb=HEAD</a></pre>
        </div>
      </p>


      <hr>
      <span>You are receiving this mail because:</span>

      <ul>
          <li>You are on the CC list for the bug.</li>
      </ul>
    </body>
</html>