[llvm-bugs] [Bug 39722] New: [AArch64] add tablegen pattern matching for "long" math instructions

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https://bugs.llvm.org/show_bug.cgi?id=39722

            Bug ID: 39722
           Summary: [AArch64] add tablegen pattern matching for "long"
                    math instructions
           Product: libraries
           Version: trunk
          Hardware: PC
                OS: All
            Status: NEW
          Severity: enhancement
          Priority: P
         Component: Backend: AArch64
          Assignee: unassignedbugs at nondot.org
          Reporter: spatel+llvm at rotateright.com
                CC: arnaud.degrandmaison at arm.com,
                    llvm-bugs at lists.llvm.org, peter.smith at linaro.org,
                    Ties.Stuij at arm.com

As discussed in https://reviews.llvm.org/D54392 :

define <4 x i16> @usubl(<8 x i8> %a, <8 x i8> %b) {
  %za = zext <8 x i8> %a to <8 x i16>
  %zb = zext <8 x i8> %b to <8 x i16>
  %xa = shufflevector <8 x i16> %za, <8 x i16> undef, <4 x i32> <i32 0, i32 1,
i32 2, i32 3>
  %xb = shufflevector <8 x i16> %zb, <8 x i16> undef, <4 x i32> <i32 0, i32 1,
i32 2, i32 3>
  %bo = sub <4 x i16> %xa, %xb
  ret <4 x i16> %bo
}

$ llc -o - uxtl.ll -mtriple=aarch64
        ushll   v0.8h, v0.8b, #0
        ushll   v1.8h, v1.8b, #0
        sub     v0.4h, v0.4h, v1.4h
        ret

This should be "usubl"? Similar matching should be added for other math ops and
types supported by the ISA.

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